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NCP1910 Datasheet(PDF) 8 Page - ON Semiconductor |
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NCP1910 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 37 page NCP1910 http://onsemi.com 8 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Unit Max Typ Min Pin Rating COMMON TO BOTH CONTROLLERS SUPPLY SECTION ICC4 IC consumption, both PFC and LLC loaded in no load conditions (PFC is 65 kHz and Rt = 70 kW (LLC is 25 kHz)) 19 − 5.9 7.2 mA ICC5 IC consumption, both PFC and LLC loaded 1 nF load conditions (PFC is 65 kHz and Rt = 70 kW (LLC is 25 kHz)) 19 − 6.9 8.6 mA ICC6 IC consumption in fault mode from Vboot (drivers disabled, Vboot > Vboot(min)) 19 − 64 300 mA ICC7 IC consumption in OFF mode from VCC (on/off pin is open) 19 − − 950 mA REFERENCE VOLTAGE Vref−out Reference voltage for external threshold setting @ Iout = 5 mA 6 4.75 5 5.25 V Vref−out Reference voltage for external threshold setting @ Iout = 5 mA – TJ = 25°C 6 4.9 5 5.1 V VrefLineReg Vcc rejection capability, Iout = 5 mA − DVCC = 1 V – TJ = 25°C 6 − 0.01 5 mV VrefLoadReg Reference variation with load changes, 1 mA < Iref < 5 mA – TJ = 25°C 6 − 1.6 7 mV Iref−out Maximum output current capability 6 5 − − mA NOTE: Maximum capacitance directly connected to VREF pin must be under 100 nF. DELAY tDEL1 Turn−on LLC delay after PFC OK signal is asserted − 10 20 30 ms tDEL2 Turn−off LLC after power good pin goes low (Note 3) − 2 5 8 ms PROTECTIONS RPull−up on/off pin pull−up resistor 4 − 5 − kW ton/off Propagation delay from on to off (ML & MU are off) (Note 4) 4 − − 1 ms Von Low level input voltage on on/off pin (NCP1910 is enabled) 4 − − 1 V Voff High level input voltage on on/off pin (NCP1910 is disabled) 4 3 − − V Vop Open voltage on on/off pin 4 − 7 − V IPG Maximum Power good pin sink current capability 3 5 − − mA VPG Power good saturation voltage for IPG = 5 mA 3 − − 350 mV IPGadj Input bias current, PGadj pin 7 − 10 − nA VPGadjH PG comparator hysteresis 7 − 100 − mV TSD Temperature shutdown (Note 4) − 140 − − °C TSDhyste Temperature Hysteresis Shutdown − − 30 − °C POWER FACTOR CORRECTION GATE DRIVE SECTION RPOH Source Resistance @ IDRV = −100 mA 18 − 9 20 W RPOL Sink Resistance @ IDRV = 100 mA 18 − 6.6 18 W tPr Gate Drive Voltage Rise Time from 1.5 V to 10.5 V (CL = 1 nF) 18 − 60 − ns tPf Gate Drive Voltage Fall Time from 10.5 V to 1.5 V (CL = 1 nF) 18 − 40 − ns 3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later, when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms. 4. Guaranteed by design. |
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