–6–

ADG406/ADG407/ADG426

REV. 0

TIMING DIAGRAMS (ADG426)

Figure 1.

Figure 1 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive;

therefore, while WR is held low, the latches are transparent and

the switches respond to the address and enable inputs. This

input data is latched on the rising edge of WR.

Figure 2.

Figure 2 shows the Reset Pulse Width, t

Off Time, t

Note: All digital input signals rise and fall times are measured

from 10% to 90% of 3 V. t

TERMINOLOGY

V

DD

Most positive power supply potential.

V

SS

Most negative power supply potential in dual

supplies. In single supply applications, it may

be connected to ground.

GND

Ground (0 V) reference.

R

ON

Ohmic resistance between D and S.

R

Difference between the R

channels.

I

Source leakage current when the switch is off.

I

Drain leakage current when the switch is off.

I

Channel leakage current when the switch

is on.

V

Analog voltage on terminals D, S.

C

Channel input capacitance for “OFF”

condition.

C

Channel output capacitance for “OFF”

condition.

C

“ON” switch capacitance.

C

IN

Digital input capacitance.

t

Delay time between the 50% and 90%

points of the digital input and switch “ON”

condition.

t

Delay time between the 50% and 90%

points of the digital input and switch “OFF”

condition.

t

TRANSITION

Delay time between the 50% and 90%

points of the digital inputs and the switch

“ON” condition when switching from one

address state to another.

t

OPEN

“OFF” time measured between 80% points of

both switches when switching from one

address state to another.

V

INL

Maximum input voltage for logic “0.”

V

INH

Minimum input voltage for logic “1.”

I

Input current of the digital input.

Crosstalk

A measure of unwanted signal which is

coupled through from one channel to another

as a result of parasitic capacitance.

Off Isolation

A measure of unwanted signal coupling

through an “OFF” channel.

Charge

A measure of the glitch impulse

Injection

transferred from the digital input to the analog

output during switching.

I

DD

Positive supply current.

I

SS

Negative supply current.

50%

50%

2V

0.8V

3V

WR

0V

3V

A0, A1, A2, (A3)

EN

0V

50%

t

RS

50%

0.8V

0

3V

0V

V

0

0V

RS

t

SWITCH

OUTPUT