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ADG412BN Datasheet(PDF) 6 Page - Analog Devices |
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ADG412BN Datasheet(HTML) 6 Page - Analog Devices |
6 / 8 page ADG411/ADG412/ADG413 REV. A –6– FREQUENCY – Hz 120 100 40 100 10M 1k 10k 100k 1M 80 60 VDD = +15V VSS = –15V VL = +5V Figure 7. Off Isolation vs. Frequency FREQUENCY – Hz 110 100 60 100 10M 1k 10k 100k 1M 90 80 70 VDD = +15V VSS = –15V VL = +5V Figure 8. Crosstalk vs. Frequency APPLICATION Figure 9 illustrates a precise, fast, sample-and-hold circuit. An AD845 is used as the input buffer while the output operational amplifier is an AD711. During the track mode, SW1 is closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capaci- tor CH. Due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The ADG411/ADG412/ ADG413 minimizes this droop due to its low leakage specifica- tions. The droop rate is further minimized by the use of a poly- styrene hold capacitor. The droop rate for the circuit shown is typically 30 µV/µs. A second switch, SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both switches will be at the same potential, they will have a differen- tial effect on the op amp AD711, which will minimize charge injection effects. Pedestal error is also reduced by the compensa- tion network RC and CC. This compensation network also re- duces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedes- tal error has a maximum value of 5 mV over the ±10 V input range. Both the acquisition and settling times are 850 ns. +15V –15V 2200pF RC 75 CC 1000pF CH 2200pF VOUT ADG411 ADG412 ADG413 SW2 SW1 S S D D +15V +5V –15V AD845 +15V –15V VIN AD711 Figure 9. Fast, Accurate Sample-and-Hold |
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