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ADM488 Datasheet(PDF) 2 Page - Analog Devices |
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ADM488 Datasheet(HTML) 2 Page - Analog Devices |
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2 / 12 page  –2– REV. 0 ADM488/ADM489–SPECIFICATIONS (VCC = +5 V 10%. All specifications TMIN to TMAX unless otherwise noted) Parameter Min Typ Max Units Test Conditions/Comments DRIVER Differential Output Voltage, VOD 5.0 V R = ∞, Figure 1 2.0 5.0 V VCC = 5 V, R = 50 Ω (RS-422), Figure 1 1.5 5.0 V R = 27 Ω (RS-485), Figure 1 1.5 5.0 V VTST = –7 V to +12 V, Figure 2, VCC = 5 V ± 5% ∆|V OD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 1 Common-Mode Output Voltage VOC 3 V R = 27 Ω or 50 Ω, Figure 1 ∆|V OC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω Output Short Circuit Current (VOUT = High) 250 mA –7 V ≤ V O ≤ +12 V Output Short Circuit Current (VOUT = Low) 250 mA –7 V ≤ V O ≤ +12 V CMOS Input Logic Threshold Low, VINL 1.4 0.8 V CMOS Input Logic Threshold High, VINH 2.0 1.4 V Logic Input Current (DE, DI) ±1.0 µA RECEIVER Differential Input Threshold Voltage, VTH –0.2 +0.2 V –7 V ≤ V CM ≤ +12 V Input Voltage Hysteresis, ∆V TH 70 mV VCM = 0 V Input Resistance 12 k Ω –7 V ≤ V CM ≤ +12 V Input Current (A, B) +1 mA VIN = 12 V –0.8 mA VIN = –7 V Logic Enable Input Current ( RE) ±1 µA CMOS Output Voltage Low, VOL 0.4 V IOUT = +4.0 mA CMOS Output Voltage High, VOH 4.0 V IOUT = –4.0 mA Short Circuit Output Current 7 85 mA VOUT = GND or VCC Three-State Output Leakage Current ±1.0 µA 0.4 V ≤ V OUT ≤ +2.4 V POWER SUPPLY CURRENT Outputs Unloaded, Receivers Enabled ICC 30 60 µA DE = 0 V (Disabled) 37 74 µA DE = 5 V (Enabled) Specifications subject to change without notice. TIMING SPECIFICATIONS Parameter Min Typ Max Units Test Conditions/Comments DRIVER Propagation Delay Input to Output TPLH, TPHL 250 2000 ns RL Diff = 54 Ω, CL1 = CL2 = 100 pF, Figure 5 Driver O/P to O/P T SKEW 100 800 ns RL Diff = 54 Ω, CL1 = CL2 = 100 pF, Figure 5 Driver Rise/Fall Time TR, TF 250 2000 ns RL Diff = 54 Ω, CL1 = CL2 = 100 pF, Figure 5 Driver Enable to Output Valid 250 2000 ns RL = 500 Ω, CL = 100 pF, Figure 2 Driver Disable Timing 300 3000 ns RL = 500 Ω, CL = 15 pF, Figure 2 Data Rate 250 kbps RECEIVER Propagation Delay Input to Output TPLH, TPHL 250 2000 ns CL = 15 pF, Figure 5 Skew |TPLH–TPHL| 100 ns Receiver Enable TEN1 10 50 ns RL = 1 kΩ, CL = 15 pF, Figure 4 Receiver Disable TEN2 10 50 ns RL = 1 kΩ, CL = 15 pF, Figure 4 Data Rate 250 kbps Specifications subject to change without notice. (V CC = +5 V 10%. All specifications T MIN to TMAX unless otherwise noted) |
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