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ADM705 Datasheet(PDF) 4 Page - Analog Devices

Part # ADM705
Description  Low Cost uP Supervisory Circuits
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADM705 Datasheet(HTML) 4 Page - Analog Devices

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REV. B
–4–
ADM705–ADM708
Manual Reset (ADM707/ADM708)
The manual reset input (
MR) allows other reset sources, such as
a manual reset switch, to generate a processor reset. The input
is effectively debounced by the timeout period (200 ms typical).
The
MR input is TTL/CMOS compatible, so it may also be
driven by any logic reset output.
VCC
RESET
MR
WDO
VRT
VRT
t
RS
t
RS
MR EXTERNALLY
DRIVEN LOW
Figure 3.
RESET, MR, and WDO Timing
Watchdog Timer (ADM705/ADM706)
The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in an
indefinite loop. An output line on the processor is used to toggle
the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(
WDO) goes low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor; therefore, if the
watchdog timer times out, an interrupt is generated. The inter-
rupt service routine should then be used to rectify the problem.
If a
RESET signal is required when a timeout occurs, the WDO
output should be connected to the manual reset input (
MR).
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. It is also cleared by
RESET
going low; therefore, the watchdog timeout period begins after
RESET goes high.
When VCC falls below the reset threshold, WDO is forced low
whether or not the watchdog timer has timed out. Normally,
this would generate an interrupt, but it is overridden by
RESET
going low.
The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The
WDO output can now be used as
a low-line output since it will only go low when VCC falls below
the reset threshold.
t
WP
WDI
WDO
RESET
t
RS
RESET EXTERNALLY
TRIGGERED BY
MR
t
WD
t
WD
t
WD
Figure 4. Watchdog Timing
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
INPUT (WDI)
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (
PFO)
WATCHDOG
OUTPUT (
WDO)
RESET
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)
ADM705/
ADM706
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
MR
VCC
250 A
VCC
WATCHDOG
TIMER
4.65V*
1.25V
Figure 1. ADM705/ADM706 Functional Block Diagram
1.25V
4.65V*
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (
PFO)
RESET
*VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
ADM707/
ADM708
RESET
GENERATOR
MR
VCC
250 A
VCC
RESET
Figure 2. ADM707/ADM708 Functional Block Diagram
CIRCUIT INFORMATION
Power-Fail
RESET Output
RESET is an active low output that provides a RESET signal to
the Microprocessor whenever the VCC input is below the reset
threshold. An internal timer holds RESET low for 200 ms after
the voltage on VCC rises above the threshold. This is intended as
a power-on RESET signal for the microprocessor. It allows time
for both the power supply and the microprocessor to stabilize
after power-up. The
RESET output is guaranteed to remain
valid (low) with VCC as low as 1 V. This ensures that the micro-
processor is held in a stable shutdown condition as the power
supply voltage ramps up.
In addition to
RESET, an active high RESET output is also
available on the ADM707/ADM708. This is the complement of
RESET and is useful for processors requiring an active high
RESET signal.


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