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ADMC200AP Datasheet(PDF) 10 Page - Analog Devices |
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ADMC200AP Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page ADMC200 REV. B –10– In the case of the ADSP-2171/2181, the system clock is internally scaled; a 10 MHz system clock will derive a 20 MHz CLKOUT. In the case of the TMS320C2x, the CLKOUT1 signal is derived from the system clock divided by a factor of 4; consequently a 50 MHz TMS320C25-50 will derive a 12.5 MHz CLKOUT1 for use by the ADMC200. Note: A pull-up resistor is required on the IRQ (Pin 18) output from the ADMC200. The STOP (Pin 47) must be tied low if not in use. SYSTEM CLOCK FREQUENCY The nominal range of the input clock for the ADMC200 is 6.25 MHz to 25 MHz. The external CLK frequency can be in- ternally divided down by 2 by writing to Bit 5 of the SYSCTRL register. If the external CLK is faster than 12.5 MHz then it is necessary to internally divide it down. REGISTER ADDRESSING Four address lines (A0 through A3) are used in conjunction with the control lines ( CS, WR, RD,) to select registers 0 through 15. The CS and RD control lines are active low. The registers are given symbolic names. Table II. Pin Function CS Enables the ADMC200 register interface (connect via chip select logic-active low) RD Places data from the internal register onto the data bus WR Loads the internal register with data on the data bus on its positive edge EN ADDRESS DECODE VDD DMS IRQ2 RD WR CLKOUT D0–D23 A0–A13 ADSP-2101/ ADSP-2105/ ADSP-2115–20MHz ADSP-2181–10MHz ADSP-2171–10MHz CS IRQ RD WR CLK D0–D11* A0–A3 ADMC200 ADDRESS BUS DATA BUS *NOTE: BY MAPPING THE ADMC200 DATA BUS TO THE TWELVE HIGHEST BITS OF THE ADSP DATA BUS, FULL-SCALE OUTPUTS FROM THE ADC CAN BE REPRESENTED BY ± 1.0 IN FIXED POINT ARITHMETIC. Figure 11. ADI Digital Signal Processor/Microcomputer EN ADDRESS DECODE VDD IS INTn STRB R/ W CLKOUT1 D0–D15 A0–A15 TMS320C20 TMS320C25-50 TMS320C25 CS IRQ RD WR CLK D0–D11 A0–A3 ADMC200 ADDRESS BUS DATA BUS Figure 12. TI Second-Generation Devices TMS320C20/ C25/C25–50 Table III. Write Registers Name A3 A2 A1 A0 Register Function RHO 0000 Load RHO ( ρ) and Start Reverse Transform PHIP1/VD 0001 Reverse Rotation Direct Input/Forward Direct Input PHIP2/VQ 0010 Reverse Rotation Direct Input/Forward Direct Input PHIP3 0011 Reverse Rotation Direct Input RHOP 0100 Load RHOP( ρ) and Start Forward Transform PWMTM 0101 PWM Master Switching Period PWMCHA 0110 PWM Channel A On-Time PWMCHB 0111 PWM Channel B On-Time PWMCHC 1000 PWM Channel C On-Time PWMDT 1001 PWM Programmable Deadtime (7-Bit Register) PWMPD 1010 PWM Pulse Deletion Value (7-Bit Register) 1011 Reserved 1100 Reserved SYSCTRL 1101 System Control 1110 Reserved 1111 Reserved |
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