ADN2809

REV. PrB Oct. .2001

- 9 -

FUNCTIONAL DESCRIPTION

Limiting Amplifier / Bypass & Loopback

The limiting amplifier has differential inputs (PIN/NIN), which

are normally AC coupled to the internal 50 ohm termination

(although DC coupling is possible). Input offset is factory

trimmed to achieve better than 6mV typical sensitivity with

minimal drift. The Quantizer Slicing level can be offset by +/-

100mV to mitigate the effect of ASE (amplified spontaneous

emission) noise by a differential voltage input of +/-0.8V

applied to ‘SLICEP/N’ inputs. If no adjustment

of the slice level is needed, SLICEP/N should be tied to VCC.

When the ‘Bypass’ input is driven to a TTL high state, the

Quantizer output is connected directly to the buffers driving the

Data Out pins, thus bypassing the clock recovery circuit (Figure

10). This feature can help the system to deal with non standard

bit rates. The loopback mode can be invoked by driving the

‘LOOPEN’ pin to a TTL high state, which facilitates system

diagnostic testing. This will connect the Test inputs (TDINP/N)

to the clock and data recovery circuit (per Figure 10). The Test

inputs can be left floating, when not in use. They accept AC or

DC coupled signal levels, or AC coupled LVDS.

Loss of Signal (LOS) Detector

The receiver front end Signal Detect circuit indicates when the

input signal level has fallen below a user adjustable threshold.

The threshold is set with a single external resistor, as illustrated

in figure 4, which assumes that the slice inputs are inactive.

If the LOS detector is used the Quantizer Slice Adjust pins must

both be tied to VCC, to avoid interaction with the LOS threshold

level. Note that it is not expected to use both LOS and Slice

Adjust at the same time: systems with optical amplifiers need

the slice adjust to evade ASE, but a loss of signal causes the

optical amplifier output to be full scale noise, thus the LOS

would not detect the failure. In this case the Loss of Lock signal

will indicate the failure.

Refer ence Clock

The ADN2809 can accept any of the following reference clock

frequencies: 19.44 MHz, 38.88MHz, 77.76MHz at

LVTTL/LVCMOS/LVPECL/LVDS levels or 155.52MHz at

LVPECL/LVDS levels via the REFCLKN/P inputs, independent

of data rate (including gigabit ethernet). The input buffer accepts

any differential signal with a peak to peak differential

amplitude of greater than 64mV (e.g. LVPECL or LVDS) or a

standard single ended low voltage TTL input, providing

maximum system flexibility. The appropriate division ratio can

be selected using the REFSEL0/1 pins, according to Table 3.

Phase noise and duty cycle of the Reference Clock are not

critical and 100ppm accuracy is sufficient.

A crystal oscillator is also provided, as an alternative to using

the REFCLKN/P input. Details of the recommended crystal are

given in Table 3.

REFSEL must be tied to VCC when the REFCLKN/P inputs are

active, or tied to VEE when the oscillator is used. No connection

between the XO pin and REFCLK input is necessary (see figure

11). Please note that the crystal should operate in series resonant

mode, which renders it insensitive to external parasitics. No

trimming capacitors are required.

Lock Detector Oper ation

The lock detector monitors the frequency difference between the

VCO and the reference clock, and de-asserts the ‘Loss of Lock’

signal when the VCO is within 500ppm of center frequency.

This enables the phase loop which then maintains phase lock,

unless the frequency error exceeds 0.1%. Should this occur, the

‘Loss of Lock’ signal is re-asserted and control returns to the

frequency loop which will re-acquire, and maintain a stable

clock signal at the output. The frequency loop requires a single

external capacitor between CF1 and CF2. The capacitor

specification is given in Table 5.

Squelch Mode

When the ‘Squelch’ input is driven to a TTL high state, both the

clock and data outputs are set to the zero state, to suppress

downstream processing. If desired, this pin can be directly

driven by the LOS (Loss-Of-Signal) or LOL (Loss-Of-Lock)

detector outputs. If the Squelch function is not required, the pin

should be tied to VEE.