ADN2850BCP250 datasheet(10/20 Pages) AD

Part #	ADN2850BCP250

Description	Nonvolatile Memory, Dual 1024 Position Programmable Resistors

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REV. B

–10–

ADN2850

Daisy-Chain Operation

The serial data output pin (SDO) serves two purposes. It can be

used to read out the contents of the wiper settings or EEMEM

values using instructions 10 and 9 respectively. If these instruc-

tions are not used, SDO can be used for daisy-chaining multiple

devices in simultaneous operations (see Figure 4). The SDO pin

contains an open-drain N-Ch FET and requires a pull-up resis-

tor if SDO function is used. Users need to tie the SDO pin of

one package to the SDI pin of the next package. Users may need

to increase the clock period because the pull-up resistor and the

capacitive loading at the SDO-SDI interface may induce time

delay to the subsequent devices (see Figure 4). If two ADN2850s

are daisy-chained, a total 48 bits of data is required. The first

24 bits (formatted 4-bit instruction, 4-bit address, and 16-bit

data) go to U2 and the second 24 bits with the same format go

to U1. The

CS should be kept low until all 48 bits are clocked into

their respective serial registers. The

CS is then pulled high to

complete the operation.

SDI

SDO

CLK

VDD

RP

2.2k

SDI

SDO

CLK

CS

U1

ADN2850

C

SS

MOSI

SCLK

U2

ADN2850

Figure 4. Daisy-Chain Configuration

DIGITAL INPUT/OUTPUT CONFIGURATION

All digital inputs are ESD protected. Digital inputs are high

impedance and can be driven directly from most digital sources.

Active at logic low,

PR and WP should be biased to V

DD if they

are not used. There are no internal pull-up resistors present on

any digital input pins. To avoid floating digital pins that may

cause false triggering in a noisy environment, pull-up resistors

should be added to these pins. However, this only applies to the

case where the device will be detached from the driving source

once it is programmed.

The SDO and RDY pins are open-drain digital outputs. Similarly,

pull-up resistors are needed if these functions are used. To optimize

the speed and power trade-off, use 2.2 k

Ω pull-up resistors.

The equivalent serial data input and output logic is shown in

Figure 5. The open-drain output SDO is disabled whenever

chip select

CS is logic high. ESD protection of the digital inputs

is shown in Figures 6a and 6b.

VALID

COMMAND

COUNTER

COMMAND

PROCESSOR

AND ADDRESS

DECODE

SERIAL

REGISTER

CLK

SDI

5V

RPULLUP

SDO

GND

PR

WP

CS

ADN2850

Figure 5. Equivalent Digital Input-Output Logic

LOGIC

PINS

VDD

GND

INPUTS

300

Figure 6a. Equivalent ESD Digital Input Protection

VDD

GND

INPUT

300

WP

Figure 6b. Equivalent

WP Input Protection

SERIAL DATA INTERFACE

The ADN2850 contains a 4-wire, SPI compatible, digital inter-

face (SDI, SDO,

CS, and CLK). The 24-bit serial word must be

loaded with MSB first, and the format of the word is shown in

Table I. The Command Bits (C0 to C3) control the operation of

the programmable resistor according to the instruction shown

in Table II. A0 to A3 are assigned for address bits. A0 is used to

address RDAC1 or RDAC2. Addresses 2 to 14 are accessible by

users. Address 15 is reserved for the factory. Table V provides an

address map of the EEMEM locations. The data bits (D0 to D9) are

the values that are loaded into the RDAC registers at instruc-

tion 11. The data bits (D0 to D15) are the values that are loaded

into the EEMEM registers at instruction 3.

The last instruction prior to a period of no programming activity

should be applied with the No Operation (NOP), instruction 0. It

is recommended to do so to ensure minimum power consumption

in the internal logic circuitry

The SPI interface can be used in two slave modes, CPHA = 1,

CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to

the control bits that dictate SPI timing in these microconverters

and microprocessors: ADuC812/ADuC824, M68HC11,

and MC68HC16R1/916R1.

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