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ADP3153 Datasheet(PDF) 11 Page - Analog Devices |
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ADP3153 Datasheet(HTML) 11 Page - Analog Devices |
11 / 12 page ADP3153 –11– REV. 0 BOARD LAYOUT A multilayer PCB is recommended with a minimum of two copper layers. One layer on top should be used for traces inter- connecting low power SMT components. The ground terminals of those components should be connected with vias to the bot- tom traces connecting directly to the ADP3153 ground pins. One layer should be a power ground plane. If four layers are possible, one additional layer should be an internal system ground plane, and one additional layer can be used for other system interconnections. When laying out the printed circuit board, the following check- list should be used to ensure proper operation of the ADP3153. Board Layout Guidelines 1. The power loop should be routed on the PCB to encompass small areas to minimize radiated switching noise energy to the control circuit and thus to avoid circuit problems caused by noise. This technique also helps to reduce radiated EMI. The power loop includes the input capacitors, the two MOSFETs, the sense resistor, the inductor and the output capacitors. The ground terminals of the input capacitors, the low side FET, the ADP3153 and the output capacitors should be connected together with short and wide traces. It is best to use an internal ground plane. 2. The PGND (power ground) pin of the ADP3153 must re- turn to the grounded terminals of the input and output ca- pacitors and to the source of the low side MOSFET with the shortest and widest traces possible. The AGND (analog ground) pin has to be connected to the ground terminals of the timing capacitor and the compensating capacitor, again with the shortest leads possible, and before it is connected to the PGND pin. 3. The positive terminal of the input capacitors must be con- nected to the drain of the high side MOSFET. The source terminal of this FET is connected to the drain of the low side FET, (whose source is connected to the ground plane direct) with the widest and shortest traces possible. To kill parasitic ringing at the input of the buck inductor due to parasitic capacitances and inductances, a small (L > 3 mm) ferrite bead is recommended to be placed in the drain lead of the low side FET. Also, to minimize dissipation of the high side FET, a low voltage 1 A Schottky diode can be connected between the input of the buck inductor and the source of the low side FET. 4. The positive terminal of the bypass capacitors of the +12 V supply must be connected to the VIN pin of the ADP3153 with the shortest leads possible. The negative terminals must be connected to the PGND pin of the ADP3153. 5. The sense pins of the ADP3153 must be connected to the sense resistor with as short traces as possible. Make sure that the two sense traces are routed together with minimum sepa- ration (<1 mm). The output side of the sense resistor should be connected to the VCC pin(s) of the CPU with as short and wide PCB traces as possible to reduce the VCC voltage drop. (Each square unit of 1 ounce Cu-trace has a resistance of ~0.53 m Ω. At 14 A, each mΩ of PCB trace resistance be- tween current sense resistor output and VCC terminal(s) of the CPU will reduce the regulated output voltage by 14 mV. The filter capacitors to ground at the sense terminals of the IC should be as close as possible (<8 mm) to the ADP3153. The common ground of the optional filter capacitors should be connected to the AGND pin of the ADP3153 with the shortest traces possible (<10 mm). 6. The microprocessor load should be connected to the output terminals of the converter with the widest and shortest traces possible. Use overlapping traces in different layers to mini- mize interconnection inductance. |
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