REV. 0

ADP3163

–11–

The critical capacitance limit for this circuit is 6.93 mF, while

the actual capacitance of the nine Rubycon capacitors is 9

×

2200

µF = 19.8 mF. In this case, the capacitance is safely above

the critical value.

Multilayer ceramic capacitors are also required for high-frequency

decoupling of the processor. The exact number of these MLC

capacitors is a function of the board layout space and parasitics.

Typical designs use twenty to thirty 10

µF MLC capacitors

located as close to the processor power pins as is practical.

Feedback Loop Compensation Design for ADOPT

Optimized compensation of the ADP3163 allows the best pos-

sible containment of the peak-to-peak output voltage deviation.

Any practical switching power converter is inherently limited by

the inductor in its output current slew rate to a value much less

than the slew rate of the load. Therefore, any sudden change of

load current will initially flow through the output capacitors,

and assuming that the capacitance of the output capacitor is

larger than the critical value defined by Equation 13, this will

produce a peak output voltage deviation equal to the ESR of the

output capacitor times the load current change.

The optimal implementation of voltage positioning, ADOPT,

will create an output impedance of the power converter that is

entirely resistive over the widest possible frequency range, includ-

ing dc, and equal to the maximum acceptable ESR of the output

capacitor array. With the resistive output impedance, the output

voltage will droop in proportion with the load current at any

load current slew rate; this ensures the optimal positioning and

allows the minimization of the output capacitor bank.

With an ideal current-mode-controlled converter, where the

average inductor current would respond without delay to the

command signal, the resistive output impedance could be

achieved by having a single-pole roll-off of the voltage gain of

the voltage-error amplifier. The pole frequency must coincide

with the ESR zero of the output capacitor bank. The ADP3163

uses constant frequency current-mode control, which is known

to have a nonideal, frequency dependent command signal to

inductor current transfer function. The frequency dependence

manifests in the form of a pair of complex conjugate poles at

one-half of the switching frequency. A purely resistive output

impedance could be achieved by canceling the complex conjugate

poles with zeros at the same complex frequencies and adding a

third pole equal to the ESR zero of the output capacitor. Such a

compensating network would be quite complicated. Fortunately, in

practice it is sufficient to cancel the pair of complex conjugate

poles with a single real zero placed at one-half of the switching

frequency. Although the end result is not a perfectly resistive

output impedance, the remaining frequency dependence causes

only a small percentage of deviation from the ideal resistive

response. The single-pole and single-zero compensation can be

previously; the capacitance and resistance of the series RC net-

work are calculated as follows:

C

CR

R

n

fR

mF

m

kkHz

k

nF

OC

OUT

OUT

T

OSC

T

=

×

−

××

=

×

Ω

−

××

Ω

=

π

π

19 8

1 5

631

3

600

6 31

44

..

..

.

Ω

(14)

zero-setting resistor in series with the compensating capacitor is:

R

n

f

C

kHz

nF

Z

OSC

OC

=

××

=

××

=Ω

ππ

3

600

4 7

338

.

(15)

The nearest standard 5% resistor value is 330

Ω. Note that this

therefore be omitted.

Power MOSFETs

In this example, six N-channel power MOSFETs must be used;

three as the main (control) switches, and the remaining three as

the synchronous rectifier switches. The main selection parameters

minimum gate drive voltage (the supply voltage to the ADP3414)

dictates whether standard threshold or logic-level threshold

ment for the power MOSFETs. When the ADP3163 is operating

in continuous mode, the simplifying assumption can be made

that in each phase one of the two MOSFETs is always conduct-

1.45 V, the duty ratio of the high-side MOSFET is:

D

V

V

V

V

HSF

OUT

IN

==

=

15

12

12 5

.

.%

(16)

The duty ratio of the low-side (synchronous rectifier) MOSFET is:

DD

LSF

HSF

=−

=

187 5

.%

(17)

The maximum rms current of the high-side MOSFET during

normal operation is:

I

I

n

D

I

I

AA

A

A

HSF MAX

O

HSF

L RIPPLE

O

()

()

.

.

.

=×

× +

×











 =

×× +

×









=

1

3

65

3

0 125

1

10 9

365

77

2

2

2

2

(18)

The maximum rms current of the low-side MOSFET during

normal operation is:

II

D

D

AA

LSF MAX

HFS M AX

LSF

HSF

()

(

)

.

.

.

.

=×

=

×=

77

0 875

0 125

20 4

(19)

dissipation. If 10% of the maximum output power is allowed for

MOSFET dissipation, the total dissipation in the eight MOSFETs

of the four-phase converter will be:

PV

I

VA

W

FET TOTAL

MIN

O

()

.

..

.

=×

×

=

××

=

01

0 1 1 394

65

9 06

(20)