ADP3402

–11–

REV. 0

RTC LDO is enabled, and the threshold is reduced to 3.0 V.

This allows the handset to start normally until the battery volt-

age decays to 3.0 V open circuit. Once the 3.2 V threshold is

exceeded, the RTC LDO is enabled. If, however, if the backup

coin cell is not connected, or is damaged or discharged below

1.5 V, the RTC LDO will not start on its own. In this situation,

the RTC LDO will be started by enabling the VCC LDO.

Once the system is started, i.e., the phone is turned on and the

VCC LDO is up and running, the UVLO function is entirely

disabled. The ADP3402 is then allowed to run down to very low

battery voltages, typically around 2 V. The battery voltage is

normally monitored by the microprocessor and usually shuts the

phone off at around 3.0 V.

If the phone is off, i.e., the VCC LDO is off, and the battery

voltage drops below 3.0 V, the UVLO circuit disables startup

and the RTC LDO. This is implemented with very low quies-

cent current, typically 3

µA, to protect the main battery against

any damage. NiMH batteries can reverse polarity if the 3-cell

battery voltage drops below 3.0 V and a current of more than

about 40

µA continues to flow. Lithium ion batteries will lose

their capacity, although the built-in safety circuits normally

present in these cells will most likely prevent any damage.

RESET

ADP3402 contains reset circuitry that is active both at power-up

and at power-down. RESET is held low at power-up. An inter-

nal power-good signal starts the reset delay. The delay is set by

an external capacitor on RESCAP:

tC

RESET

RESCAP

=×

10

.

ms/nF

A 100 nF capacitor will produce a 100 ms reset time. At power-

off, RESET will be kept low to prevent any spurious microproces-

sor starts. The current capability of RESET is low (a few hundred

nA) when VCC is off, to minimize power consumption. There-

fore, RESET should only be used to drive a single CMOS input.

When VCC is on, RESET will drive about 15

µA.

Overtemperature Protection

The maximum die temperature for ADP3402 is 125

temperature exceeds 160

except the RTC LDO, which has very limited current capabilities.

The LDOs will not be re-enabled before the die temperature is

below 125

and CHRON. This ensures that the handset will always power-off

before the ADP3402 exceeds its absolute maximum thermal ratings.

APPLICATIONS INFORMATION

Input Capacitor Selection

For the input voltage, VBAT, of the ADP3402, a local bypass

capacitor is recommended. Use a 5

µF to 10 µF, low ESR capaci-

tor. Multilayer ceramic chip capacitors provide the best combina-

tion of low ESR and small size, but may not be cost effective. A

lower cost alternative may be to use a 5

µF to 10 µF tantalum

capacitor with a small (1

µF to 2 µF) ceramic in parallel.

LDO Capacitor Selection

The performance of any LDO is a function of the output capaci-

tor. The digital and analog LDOs require a 2.2

µF capacitor and

the TCXO LDO requires a 0.22

µF capacitor. Larger values

may be used, but the overshoot at startup will increase slightly.

If a larger output capacitor is desired, be sure to check that the

overshoot and settling time are acceptable for the application.

All the LDOs are stable with a wide range of capacitor types and

ESR due to Analog Devices’ anyCAP technology. The ADP3402

is stable with extremely low ESR capacitors (ESR ~ 0), such as

multilayer ceramic capacitors, but care should be taken in their

selection. Note that the capacitance of some capacitor types show

wide variations over temperature or with dc voltage. A good quality

dielectric, X7R or better, is recommended.

The RTC LDO has a rechargeable coin cell or an electric double-

layer capacitor as a load, but a 0.1

µF ceramic capacitor is recom-

mended for stability and best performance.

Charge Pump Capacitor Selection

For the input (SIMBAT) and output (VSIM) of the SIM charge

pump, use 10

µF low ESR capacitors. The use of low ESR capaci-

tors improves the noise and efficiency of the SIM charge pump.

Multilayer ceramic chip capacitors provide the best combination of

low ESR and small size but may not be cost effective. A lower cost

alternative may be to use a 10

µF tantalum capacitor with a small

(1

µF to 2 µF) ceramic capacitor in parallel.

For the lowest ripple and best efficiency, use a 0.1

µF, ceramic

capacitor for the charge pump flying capacitor (CAP+ and CAP–).

A good quality dielectric, such as X7R is recommended.

Setting the Charger Turn-On Threshold

The ADP3402 can be turned on when the charger input exceeds

a programmable threshold voltage. The charger’s threshold and

hysteresis are set by selecting the values for R1 and R2 shown in

Figure 15.

The turn-on threshold for the charger is calculated using:

V

RR

RR

RV

CHR

HYS

HYS

T

=

+

×

×









+

















×

2

2

11

CHRON hysteresis resistance.

The hysteresis is determined using:

V

V

R

R

HYS

T

HYS

=× 1

Combining the above equations and solving for R1 and R2 gives

the following formulas:

R

R

V

V

HYS

T

HYS

1

=×

R

RR

V

V

RR

HYS

CHR

T

HYS

2

1

11

=

×

−









×−

Example: R1 = 10 k

Ω and R2 = 30.2 kΩ gives a charger thresh-

old (not counting the drop in the power Schottky diode) of

3.5 V

± 160 mV with a 200 mV ± 30 mV hysteresis.

Charger Diode Selection

The diode shown in Figure 15 is used to prevent the battery from

discharging into the charger turn-on setting resistors, R1 and R2. A

Schottky diode is recommended to minimize the voltage difference

from the charger to the battery and the power dissipation. Choose

a diode with a current rating high enough to handle both the bat-

tery charging current and the current the ADP3402 will draw if

powered up during charging. The battery charging current is de-

pendent on the battery chemistry, and the charger circuit. The

ADP3402 current will be dependent on the loading.