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ADSP-2171KST-133 Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-2171KST-133 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 52 page  REV. A –8– ADSP-2171/ADSP-2172/ADSP-2173 Program Memory Interface The on-chip program memory address bus (PMA) and the on- chip program memory data bus (PMD) are multiplexed with on-chip DMA and DMD buses, creating a single external data bus and a single external address bus. The 14-bit address bus directly addresses up to 16K words. 10K words of memory for ADSP-217x with optional 8K ROM and 2K words of memory for the non-ROM version are on-chip. The data bus is bidirec- tional and 24 bits wide to external program memory. Program memory may contain code and data. The program memory data lines are bidirectional. The program memory select (PMS) signal indicates access to the program memory and can be used as a chip select signal. The write (WR) signal indicates a write operation and is used as a write strobe. The read (RD) signal indicates a read operation and is used as a read strobe or output enable signal. The ADSP-217x writes data from its 16-bit registers to the 24- bit program memory using the PX register to provide the lower eight bits. When it reads data (not instructions) from 24-bit pro- gram memory to a 16-bit data register, the lower eight bits are placed in the PX register. Program Memory Maps ADSP-217x Program memory can be mapped in two ways, depending on the state of the MMAP pin. Figure 5 shows the different configura- tions. When MMAP = 0, internal RAM occupies 2K words be- ginning at address 0x0000. In this configuration, the boot loading sequence (described in “Boot Memory Interface”) is au- tomatically initiated when RESET is released. 37FF 3800 3FFF 0000 MMAP = 1 BMODE = 0 2K EXTERNAL 27FF 2800 8K INTERNAL ROM (ROMENABLE = 1) OR 4K EXTERNAL 2K INTERNAL RAM 07FF 0800 8K EXTERNAL (ROMENABLE = 0) 2K INTERNAL RAM NOT BOOTED 6K EXTERNAL 3FFF 0000 27FF 2800 07FF 0800 MMAP = 1 BMODE = 1 8K INTERNAL ROM (ROMENABLE DEFAULTS TO 1 DURING RESET) MMAP = 0 BMODE = 0 or 1 2K INTERNAL RAM BOOTED 6K EXTERNAL 3FFF 0000 27FF 2800 07FF 0800 OR 8K EXTERNAL (ROMENABLE = 0) 8K INTERNAL ROM (ROMENABLE = 1) Figure 5. ADSP-217x Memory Maps When MMAP = 1, words of external program memory begin at address 0x0000 and internal RAM is located in the upper 2K words, beginning at address 0x3800. In this configuration, pro- gram memory is not loaded although it can be written to and read from under program control. The optional ROM always resides at locations PM[0x0800] through PM[0x27FF] regardless of the state of the MMAP pin. The ROM is enabled by setting the ROMENABLE bit in the Data Memory Wait State control register, DM[0x3FFE]. When the ROMENABLE bit is set to 1, addressing program memory in this range will access the on-chip ROM. When set to zero, addressing program memory in this range will access external program memory. The ROMENABLE bit is set to 0 on chip re- set unless MMAP and BMODE = 1. The program memory interface can generate 0 to 7 wait states for external memory devices; default is to 7 wait states after RESET . Boot Memory Interface The ADSP-217x can load on-chip memory from external boot memory space. The boot memory space consists of 64K by 8-bit space, divided into eight separate 8K by 8-bit pages. Three bits in the system control register select which page is loaded by the boot memory interface. Another bit in the system control regis- ter allows the user to force a boot loading sequence under soft- ware control. Boot loading from page 0 after RESET is initiated automatically if MMAP = 0. The boot memory interface can generate 0 to 7 wait states; it defaults to 7 wait states after RESET. This allows the ADSP- 217x to boot from a single low cost EPROM such as a 27C256. Program memory is booted one byte at a time and converted to 24-bit program memory words. The BMS and RD signals are used to select and to strobe the boot memory interface. Only 8-bit data is read over the data bus, on pins D8–D15. To accommodate addressing up to eight pages of boot memory, the two MSBs of the data bus are used in the boot memory interface as the two MSBs of the boot space address. The ADSP-2100 Family Assembler and Linker support the cre- ation of programs and data structures requiring multiple boot pages during execution. RD and WR must always be qualified by PMS, DMS, or BMS to ensure the correct program, data, or boot memory accessing. HIP Booting The ADSP-217x can also boot programs through its Host Inter- face Port. If BMODE = 1 and MMAP = 0, the ADSP-217x boots from the HIP. If BMODE = 0, the ADSP-217x boots through the data bus (in the same way as the ADSP-2101), as described above in “Boot Memory Interface.” For additional in- formation about HIP booting, refer to the ADSP-2100 Family User’s Manual, Chapter 7, “Host Interface Port.” The ADSP-2100 Family Development Software includes a util- ity program called the HIP Splitter. This utility allows the cre- ation of programs that can be booted via the ADSP-217x’s HIP, in a similar fashion as EPROM-bootable programs generated by the PROM Splitter utility. |
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