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ADSP-2171BS-133 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-2171BS-133 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 52 page  REV. A –10– ADSP-2171/ADSP-2172/ADSP-2173 Bus Request & Bus Grant The ADSP-217x can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-217x is not performing an external memory access, then it responds to the active BR input in the following processor cycle by: • three-stating the data and address buses and the PMS, DMS, BMS , RD, WR output drivers, • asserting the bus grant (BG) signal, and • halting program execution. If the Go Mode is enabled, the ADSP-217x will not halt pro- gram execution until it encounters an instruction that requires an external memory access. If the ADSP-217x is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes, which can be up to eight cycles later depending on the number of wait states. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory ac- cesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program ex- ecution from the point where it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The new Bus Grant Hang logic and associated BGH pin allow the ADSP-217x to operate in a multiprocessor environment with a minimal number of “wasted” processor cycles. The bus grant hang pin is asserted when the ADSP-217x desires a cycle, but cannot execute it because the bus is granted to some other processor. With the BGH signal, the other processor(s) in the system can be alerted that the ADSP-217x is hung and release the bus by deasserting bus request. Once the bus is released the ADSP-217x executes the external access and deasserts BGH. This is a signal to the other processors that external memory is now available. ADSP-217X REGISTERS Figure 7 summarizes all the registers in the ADSP-217x. Some registers store values. For example, AX0 stores an ALU oper- and; I4 stores a DAG2 pointer. Other registers consist of control bits and fields, or status flags. For example, ASTAT contains status flags from arithmetic operations, and fields in DWAIT control the numbers of wait states for different zones of data memory. A secondary set of registers in all computational units allows a single-cycle context switch. The bit and field definitions for control and status registers are given in the rest of this section, except for IMASK, ICNTL and IFC, which are defined earlier in this data sheet. The system control register, DWAIT register, timer registers, HIP control registers, HIP data registers, and SPORT control registers are all mapped into data memory; that is, registers are accessed by reading and writing data memory locations rather than register names. The particular data memory address is shown with each memory-mapped register. Register bit values shown on the following pages are the default bit values after reset. If no values are shown, the bits are indeter- minate at reset. Reserved bits are shown in gray; these bits should always be written with zeros. MAC MR0 MR1 MF MR2 MX0 MX1 MY0 MY1 DMA BUS PMA BUS DMD BUS PMD BUS 14 POWERDOWN CONTROL LOGIC PROGRAM ROM 8K X 24 PROGRAM SRAM 2K X 24 DAG 2 M4 M5 M6 M7 L4 L5 L6 L7 I4 I5 I6 I7 DAG 1 M0 M1 M2 M3 L0 L1 L2 L3 I0 I1 I2 I3 PROGRAM SEQUENCER COUNT STACK 4 X 14 CNTR OWRCNTR STATUS STACK 12 X 25 IMASK MSTAT ASTAT SSTAT ICNTL IFC PC STACK 16 X 14 LOOP STACK 4 X 18 DM WAIT CONTROL SYSTEM CONTROL 0x3FFF 0x3FFE HOST INTERFACE PORT DATA STATUS HMASK 0x3FE0-0x3FE5 0x3FE6-0x3FE7 0x3FE8 ALU AF AR AX0 AY1 AY0 AX1 SHIFTER SR0 SR1 SI SE SB SPORT 1 CONTROL REGISTERS 0x3FF2-0x3FEF RX1 TX1 SPORT 0 CONTROL REGISTERS 0x3FFA-0x3FF3 RX0 TX0 PX TIMER TPERIOD TCOUNT TSCALE 0x3FFD 0x3FFC 0x3FFB FLAGS 14 16 24 DATA SRAM 2K X 16 Figure 7. ADSP-217x Registers Control Register |
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