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ADSP-21MOD980N-000 Datasheet(PDF) 4 Page - Analog Devices |
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ADSP-21MOD980N-000 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 42 page  4 6/2001 REV. PrB For current information contact Analog Devices at (800) ANALOGD ADSP-21mod980N PRELIMINARY TECHNICAL DATA ARCHITECTURE OVERVIEW Figure 2 on page 4 is a functional block diagram of the ADSP-21mod980N. It contains eight independent digital signal processors. Every modem processor has: • A DSP core • 256K bytes of RAM • Two serial ports • An IDMA host. The signals of each modem processor are accessed through the external pins of the ADSP-21mod980N. Some signals are bussed with the signals of the other processors and are accessed through a single external pin. Other signals remain separate and they are accessed through separate external pins for each processor. The arrangement of the eight modem processors in the ADSP-21mod980N makes one basic configuration possi- ble: a slave configuration. In this configuration, the data pins of all eight processors connect to a single bus structure. Figure 2. ADSP-21mod980N Functional Block Diagram IAD<15:0>, IDM A CNTL P F<0:2>/M OD E A:C 20 3 2188N 2188N 2188N 2188N 2188N 17 2188N 4 4 8 4 2188N 2188N 20 SPORT1 SPORT0A CLKIN EMULATOR S UBTO TAL = 177 S IG NAL BALLS SIGNALS RO UTED TO EACH RESPECTIVE DIE 8 BG <8:1> 8 BR <8:1> EE <8:1> 8 IS <8:1> 8 RESET <8:1> 8 CLKOUT <8:1> 8 TFS 0 <8:1> 8 DT1 <8:1> 8 INTE RRUP TS < 8:1> 32 22 V DDINT 44 VDDE XT S UBTO TAL = 175 P OW E R BALLS TOTAL = 352 BALLS 109 GND DATA< 23:8>, A<0 > IAD <15:0>, IDM A CNTL SPORT0B IDM A CNTL = IAL, IRD, IW R, IACK INTE RRUP TS = IRQE (P F4), IRQL 0(P F5), IRQL1(P F6), IRQ2(P F7) EM ULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK ELOUT, ERESET SPORT0A, SPO RT 0B = RFS 0, DR0, DT0, S CKL0 SPORT1 = RFS1, TFS 1, DR1, SCKL1 NOTE : 1. P W D AND P F3/M ODE D ARE TIE D HIGH DSP 1 DSP 2 DSP 3 DSP 4 DSP 5 DSP 6 DSP 7 DSP 8 |
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