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ADV7175AKS Datasheet(PDF) 10 Page - Analog Devices |
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ADV7175AKS Datasheet(HTML) 10 Page - Analog Devices |
10 / 52 page ADV7175A/ADV7176A –10– REV. B PIN FUNCTION DESCRIPTIONS Pin Input/ No. Mnemonic Output Function 1, 11, 20, 28, 30 VAA P Power Supply (+3 V to +5 V). 10, 19, 21, 29, 43 GND G Ground Pin. 15 HSYNC I/O HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master Mode) or accept (Slave Mode) Sync signals. 16 FIELD/ VSYNC I/O Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output (Master Mode) or accept (Slave Mode) these control signals. 17 BLANK I/O Video Blanking Control Signal. The pixel inputs are ignored when this is logic level “0.” This signal is optional. 18 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address. 22 RESET I The input resets the on chip timing generator and sets the ADV7175A/ ADV7176A into default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 × composite and S-Video out and all DACs powered on. 23 SCLOCK I MPU Port Serial Interface Clock Input. 24 SDATA I/O MPU Port Serial Data Input/Output. 25 COMP O Compensation Pin. Connect a 0.1 µF capacitor from COMP to V AA. For Optimum Dynamic Performance in Low Power Mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF. 26 DAC C O RED/S-Video C/V Analog Output. 27 DAC D O GREEN/S-Video Y/Y Analog Output. 31 DAC B O BLUE/Composite/U Analog Output. 32 DAC A O PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286 mV) for NTSC and 1300 mV for PAL. 33 VREF I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). 34 RSET I A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals. 35 SCRESET/RTC I This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a subcarrier reset pin, in which case a high to low transition on this pin will reset the subcarrier to Field 0. Alternatively it may be configured as a Real Time Control (RTC) input. 36 TTXREQ/GND O Teletext Data Request Signal/Defaults to GND when Teletext not selected (enables backward compatibility to ADV7175/ADV7176). 37 TTX/VAA I Teletext Data/Defaults to VAA when Teletext not selected (enables backward compatibility to ADV7175/ADV7176). 38–42 P0–P15 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 2–9, 12–14 16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB. 44 CLOCK I TTL Clock Input. Requires a stable 27 MHz reference Clock for standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. |
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