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ADS4222 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS4222 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 66 page  ADS42B49 www.ti.com SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013 Table 2. LVDS Timings at Lower Sampling Frequencies(1) CLOCK PROPAGATION SETUP TIME (ns) HOLD TIME (ns) DELAY (ns) SAMPLING tSU_RISE tSU_FALL tHO_RISE tHO_FALL tPDI FREQUENCY (MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX 100 0.36 0.72 0.67 1.10 3.37 3.80 3.02 3.48 10.4 11.8 13.1 125 0.35 0.72 0.66 1.08 2.43 2.82 2.09 2.51 9.4 10.8 12.1 150 0.35 0.70 0.66 1.07 1.77 2.15 1.47 1.86 8.8 10.1 11.5 175 0.35 0.70 0.63 1.07 1.32 1.67 1.00 1.40 8.3 9.7 11.0 200 0.38 0.70 0.68 1.08 0.93 1.29 0.66 1.04 8.0 9.4 10.8 230 0.33 0.69 0.67 1.06 0.63 0.97 0.35 0.74 7.7 9.1 10.5 (1) Setup and hold values in DDR LVDS mode belong to delayed output clock by writing register 42h, value 30h. Table 3. CMOS Timings at Lower Sampling Frequencies SETUP TIME(1) HOLD TIME(1) CLOCK PROPAGATION DELAY SAMPLING (tSU, ns) (tHO, ns) (tPDI, ns) FREQUENCY (MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX 100 3.91 4.40 3.68 4.18 9.5 11.5 13.3 125 2.81 3.40 2.73 3.14 8.5 10.5 12.3 150 2.00 2.64 2.09 2.52 7.9 9.9 11.7 175 1.43 2.14 1.67 2.06 7.6 9.4 11.4 200 1.01 1.76 1.25 1.68 6.4 8.9 11.1 (1) In CMOS mode, setup time is measured from the beginning of data valid to the mid-point of the CLKOUT rising edge, whereas hold time is measured from the mid-point of the CLKOUT rising edge to data becoming invalid. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADS42B49 |
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