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SN65DSI83ZQER Datasheet(PDF) 4 Page - Texas Instruments

Part # SN65DSI83ZQER
Description  MIPI DSI BRIDGE TO FLATLINK LVDS Single Channel DSI to Single-Link LVDS Bridge
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN65DSI83ZQER Datasheet(HTML) 4 Page - Texas Instruments

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SN65DSI83
SLLSEC1D – SEPTEMBER 2012 – REVISED DECEMBER 2012
www.ti.com
PIN FUNCTIONS (continued)
PIN
DESCRIPTION
SIGNAL
PIN
I/O
Local I2C Interface Target Address Select. See Table 2. In normal operation
CMOS
this pin is an input. When the ADDR pin is programmed high, it should be tied
ADDR
A1
Input/Output
to the same 1.8 V power rails where the SN65DSI83 VCC 1.8 V power rail is
connected.
CMOS Input with
EN
B1
Chip Enable and Reset. Device is reset (shutdown) when EN is low.
pullup (Failsafe)
Optional External Reference Clock for LVDS Pixel Clock. If an External
Reference Clock is not used, this pin should be pulled to GND with an external
REFCLK
H2
CMOS Input
resistor. The source of the reference clock should be placed as close as
(Failsafe)
possible with a series resistor near the source to reduce EMI.
SCL
H1
Local I2C Interface Clock.
Open Drain
SDA
J1
Input/Output
Local I2C Interface Bi-directional Data Signal.
(Failsafe)
IRQ
J9
CMOS Output
Interrupt Signal.
A2, A8, B9, D5,
GND
Reference Ground.
E4, F4, F5, H9
A9, B8, D6, E5,
VCC
Power Supply
1.8 V Power Supply.
E6, F6, J2
1.1 V Output from Voltage Regulator. This pin must have a 1 µF external
VCORE
J8
capacitor to GND.
ORDERING INFORMATION
PART NUMBER
PART MARKING
PACKAGE / SHIPPING
SN65DSI83ZQER
DSI83
64-Ball PBGA, Reel
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply Voltage Range
VCC
-0.3
2.175
V
CMOS Input Terminals
-0.5
2.175
V
Input Voltage Range
DSI Inpt Terminals (DA x P/N, DB x P/N)
-0.4
1.4
V
Storage Temperature
TS
-65
105
°C
Human Body Model (2)
±2
kV
Electrostatic discharge
Charged-device model (3)
±500
V
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Tested in accordance with JEDEC Standard 22, Test Method A114-B
(3)
Tested in accordance with JEDEC Standard 22, Test Method C101-A
4
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: SN65DSI83


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