9

8

7

6

5

4

3

2

1

A

ADDR

B_Y0P

B_Y1N

B_Y2N

B_CLKN

B_Y3N

GND

VCC

EN

B_Y1P

B_Y2P

B_CLKP

B_Y3P

VCC

GND

A_Y0P

A_Y0N

GND

VCC

A_Y1P

A_Y1N

GND

VCC

VCC

A_Y2P

A_Y2N

GND

GND

VCC

A_CLKP

A_CLKN

A_Y3P

A_Y3N

SCL

REFCLK

DA0P

DA1P

DACP

DA2P

DA3P

RSVD1

GND

SDA

VCC

DA0N

DA1N

DACN

DA2N

DA3N

VCORE

IRQ

GND

RSVD2

B

C

D

E

F

G

H

J

NC

GND

VCC

GND

VCC

VCC

GND

GND

VCC

SCL

SDA

NC

NC

NC

NC

NC

NC

NC

NC

NC

B_Y0N

SN65DSI84

www.ti.com

SLLSEC2C – SEPTEMBER 2012 – REVISED DECEMBER 2012

ZQE PACKAGE

(TOP VIEW)

To minimize the power supply noise floor, provide good decoupling near the SN65DSI84 power pins. The use of four

ceramic capacitors (2x 0.1

μF and 2x 0.01 μF) provides good performance. At the least, it is recommended to install

one 0.1

μF and one 0.01 μF capacitor near the SN65DSI84. To avoid large current loops and trace inductance, the

trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor

underneath the SN65DSI84 on the bottom of the PCB is often a good choice.

PIN FUNCTIONS

PIN

DESCRIPTION

SIGNAL

PIN

I/O

DA0P, DA0N

H3, J3

MIPI® D-PHY Channel A Data Lane 0; data rate up to 1 Gbps.

DA1P, DA1N

H4, J4

MIPI® D-PHY Channel A Data Lane 1; data rate up to 1 Gbps.

LVDS Input (HS)

DA2P, DA2N

H6, J6

CMOS Input (LS)

MIPI® D-PHY Channel A Data Lane 2; data rate up to 1 Gbps.

(Failsafe)

DA3P, DA3N

H7, J7

MIPI® D-PHY Channel A Data Lane 3; data rate up to 1 Gbps.

DACP, DACN

H5, J5

MIPI® D-PHY Channel A Clock Lane; operates up to 500 MHz.

C2, C1, D2, D1,

NC

F2, F1, G2, G1,

No connects.

These pins should not be connected to any signal, power or ground.

E2, E1

Copyright © 2012, Texas Instruments Incorporated

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