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VCA5807 Datasheet(PDF) 9 Page - Texas Instruments |
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VCA5807 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 64 page  VCA5807 www.ti.com SLOS727 – DECEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5V, AVDD = 3.3V, AC-coupled with 0.1µF at INP and bypassed to ground with 15nF at INM, No active termination, VCNTL= 0V, fIN= 5MHz, LNA = 18dB, PGA = 24dB, LPF Filter = 15MHz, low noise mode, VOUT= –1dBFS (1.8VPP), single-ended VCNTL mode, VCNTLM = GND, 2 k Ω load (ADC Rin), internal 500Ω CW feedback resistor, CMOS CW clocks, at ambient temperature TA = 25°C, unless otherwise noted. Min and max values are specified across full-temperature range with AVDD_5V=5V, AVDD=3.3V PARAMETER TEST CONDITION MIN TYP MAX UNITS CW SUMMING AMPLIFIER VCMO Common-mode voltage Summing amplifier inputs/outputs 1.5 V Summing amplifier output 4 VPP 100Hz 2 nV/rtHz Input referred voltage noise (3) 1kHz 1.2 nV/rtHz 2KHz-100MHz 1 nV/rtHz 100Hz 7 pA/rtHz Input referred current noise (3) 1kHz 3 pA/rtHz 10KHz-100MHz 2.5 pA/rtHz Unit gain bandwidth 200 MHz Max output current Linear operation range 20 mAPP POWER DISSIPATION AVDD Voltage 3.15 3.3 3.6 V AVDD_5V Voltage 4.75 5 5.5 V TGC low noise mode, no signal 203 235 TGC medium power mode, no signal 126 TGC low power mode, no signal 99 CW-mode, no signal 147 172 AVDD (3.3V) Current mA TGC low noise mode, 500mVPP Input,1% duty cycle 210 TGC medium power mode, 500mVPP Input, 1% duty cycle 133 TGC low power, 500mVPP Input, 1% duty cycle 105 CW-mode, 500mVPP Input 375 TGC mode no signal 25.5 35 CW Mode no signal, 16X clock = 32MHz 32 AVDD_5V Current mA TGC mode, 500mVPP Input,1% duty cycle 16.5 CW-mode, 500mVPP Input 42.5 TGC low noise mode, no signal 99 121 TGC medium power mode, no signal 68 TGC low power mode, no signal 55.5 VCA Power dissipation mW/CH TGC low noise mode, 500mVPP input,1% duty cycle 102.5 TGC medium power mode, 500mVPP Input, 1% duty cycle 71 TGC low power mode, 500mVPP input,1% duty cycle 59.5 CW Power dissipation No signal, CW Mode no signal, 16X clock = 32MHz 80 mW/CH 500mVPP input, 16X clock = 32MHz 173 Power dissipation in power down mode PDN_FAST = High 12.5 mW/CH Complete power-down PDN_Global=High 0.6 2 Power-down response time Time taken to enter power down 1 µs 2µs+1% of PDN VCA power down µs time Power-up response time Complete power down 2.5 ms fin = 5MHz, at 50mVpp noise at 1KHz on supply (4) –65 dBc Power supply modulation ratio, AVDD and AVDD_5V (TGC Mode) fin = 5MHz, at 50mVPP noise at 50KHz on supply (4) –65 dBc f = 10kHz, VCNTL = 0V (high gain), AVDD –40 dBc Power supply rejection ratio (TGC Mode) f = 10kHz, VCNTL = 0V (high gain), AVDD_5V –55 dBc f = 10kHz, VCNTL = 1V (low gain), AVDD –50 dBc fin = 5MHz, 1-20 KHz 100mVpp noise on the AVDD -57 dBc Power supply modulation ratio (CW Mode with 8 mixers active) fin = 5MHz, 1-20 KHz 100mVpp noise on the AVDD_5V -59 dBc fin = 5MHz, 5.001-5.02 MHz 100mVpp noise on the AVDD -75 dBc Power supply rejection ratio (CW Mode with 8 mixers active) fin = 5MHz, 5.001-5.02 MHz 100mVpp noise on the AVDD_5V -40 dBc (3) By simulation. (4) PSMR specification is with respect to RF signal amplitude. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: VCA5807 |
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