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BQ24157 Datasheet(PDF) 3 Page - Texas Instruments

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Part # BQ24157
Description  Fully Integrated Switch-Mode Charger With USB Compliance and USB-OTG Support
Download  39 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

BQ24157 Datasheet(HTML) 3 Page - Texas Instruments

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B1
C1
D1
SW
PMID
PGND
B2
C2
D2
SW
PMID
PGND
B3
C3
D3
SW
PMID
PGND
B4
C4
D4
STAT
SDA
OTG
A1
VBUS
A2
VBUS
A3
BOOT
A4
SCL
E1
CSIN
E2
CD
E3
VREF
E4
CSOUT
bq24157
(Top View)
bq24157
www.ti.com
SLUSB80 – SEPTEMBER 2012
PIN LAYOUT (20-Bump YFF Package)
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1
μF) to PGND if there are
CSOUT
E4
I
long inductive leads to battery.
Charger input voltage. Bypass it with a 1-
μF ceramic capacitor from VBUS to PGND. It also provides power to the
VBUS
A1, A2
I/O
load during boost mode .
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-
μF
PMID
B1, B2, B3
I/O
capacitor from PMID to PGND.
SW
C1, C2, C3
O
Internal switch to output inductor connection.
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10-nF ceramic capacitor (voltage rating
BOOT
A3
I/O
10 V) from BOOT pin to SW pin.
PGND
D1, D2, D3
Power ground
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-
μF ceramic capacitor
CSIN
E1
I
to PGND is required.
SCL
A4
I
I2C interface clock. Connect a 10-k
Ω pullup resistor to 1.8V rail (VAUX= VCC_HOST)
SDA
B4
I/O
I2C interface data. Connect a 10-k
Ω pullup resistor to 1.8V rail (VAUX= VCC_HOST)
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-
μs pulse is
STAT
C4
O
sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or
communicate with a host processor.
Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND. External load on VREF is
VREF
E3
O
not recommended.
Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high impedance to
CD
E2
I
GND.
Boost mode enable control or input current limiting selection pin. When OTG is in active status, the device is forced to
operate in boost mode. It has higher priority over I2C control and can be disabled using the control register. At POR
OTG
D4
I
while in default mode, the OTG pin is used as the input current limiting selection pin. The I2C register is ignored at
startup. When OTG=High, IIN_LIMIT = 500mA and when OTG = Low, IIN_LIMIT = 100mA.
ORDERING INFORMATION(1)
PART NUMBER
MARKING
MEDIUM
QUANTITY
bq24157YFFR
bq24157A
Tape and Reel
3000
bq24157YFFT
bq24157A
Tape and Reel
250
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2012, Texas Instruments Incorporated
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