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TPS43061RTER Datasheet(PDF) 6 Page - Texas Instruments |
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TPS43061RTER Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 32 page  TPS43060 TPS43061 SLVSBP4A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 4.5 to 38 V, TJ = -40ºC to +150ºC, unless otherwise noted. Typical values are at TA = 25ºC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tCLK-min Minimum input clock pulse width PLL = 500 kHz 14 60 ns vCLK-H RT/CLK high threshold 1.78 2 V RT/CLK low threshold 0.4 1.35 V fCLK PLL frequency sync range 300 1000 kHz tPLLIN PLL lock in time 100 250 µs tPLLEXIT Last RT/CLK falling edge to return to resistor timing mode if CLK is not present 140 250 µs POWER SWITCH DRIVERS VIN = 12 V - 40 V 2 TPS43060 Ω VIN = 4.5 V 3 LDRV pull-up resistance VIN = 12 V - 40 V 2.5 TPS43061 Ω VIN = 4.5 V 3 RLDRV VIN = 12 V - 40 V 1.2 TPS43060 Ω VIN = 4.5 V 2 LDRV pull-down resistance VIN = 12 V - 40 V 1.6 TPS43061 Ω VIN = 4.5 V 2 VIN = 12 V - 40 V 2 TPS43060 Ω VIN = 4.5 V 2.8 HDRV pull-up resistance VIN = 12 V - 40 V 5 TPS43061 Ω VIN = 4.5 V 5.5 RHDRV VIN = 12 V - 40 V 1.2 TPS43060 Ω VIN = 4.5 V 1.9 HDRV pull-down resistance VIN = 12 V - 40 V 3 TPS43061 Ω VIN = 4.5 V 3.7 TPS43060 15 High side gate rise time, 10% to CLOAD = 2.2 nF, tHR ns 90% VIN = 12 V - 40 V TPS43061 20 TPS43060 10 High side gate fall time, 90% to CLOAD = 2.2 nF, tHF ns 10% VIN = 12 V - 40 V TPS43061 15 TPS43060 15 Low side gate rise time, 10% to CLOAD = 2.2 nF, tLR ns 90% VIN = 12 V - 40 V TPS43061 20 TPS43060 10 Low side gate fall time, 90% to CLOAD = 2.2 nF, tLF ns 10% VIN = 12 V - 40 V TPS43061 15 BOOT diode forward voltage VF TPS43061 IF = 10 mA, TA = 25ºC 0.75 V drop IBOOT BOOT pin leakage current TPS43061 Vr = 60 V 0.1 µA tON LDRV minimum on pulse width fSW = 500 kHz 100 ns tOFF LDRV minimum off pulse width fSW = 500 kHz 250 ns TPS43060, VIN = 12V 65 ns CLOAD = open, Time delay between LDRV VIN = 4.5V 75 ns fSW = 500 kHz fall(50%) to HDRV rise (50%), TPS43061, VIN = 12V 65 ns tnon-overlap1 CLOAD = open, VIN = 4.5V 75 ns fSW = 500 kHz tdelay TPS43060, VIN = 12V 65 ns CLOAD = open, Time delay between HDRV fall VIN = 4.5V 75 ns fSW = 500 kHz (50%) to LDRV rise (50%), tnon- TPS43061, VIN = 12V 65 ns overlap2 CLOAD = open, VIN = 4.5V 75 ns fSW = 500 kHz 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS43060 TPS43061 |
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