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TPS61310YFF Datasheet(PDF) 6 Page - Texas Instruments |
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TPS61310YFF Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 57 page  Sr P Sr tfDA trDA thd;DAT tsu;STA thd;STA tsu;DAT tsu;STO trCL1 tfCL tHIGH tLOW tLOW tHIGH trCL trCL1 =MCSCurrentSourcePull-Up =R(P) ResistorPull-Up SDAH SCLH NoteA:FirstrisingedgeoftheSCLHsignalafterSrandaftereachacknowledgebit. SeeNoteA SeeNoteA tf tLOW tr thd;STA thd;DAT tsu;DAT tf HIGH tsu;STA S Sr P S thd;STA tr tBUF tsu;STO SDA SCL TPS61310, TPS61311 SLVS978C – MARCH 2010 – REVISED NOVEMBER 2012 www.ti.com I 2C INTERFACE TIMING CHARACTERISTICS(1) (continued) PARAMETER TEST CONDITIONS MIN MAX UNIT Standard mode 20 + 0.1 CB 1000 ns Rise Time of SCL Signal After a Fast mode 20 + 0.1 CB 300 ns tRCL1 Repeated START Condition and After High-speed mode, CB – 100pF max 10 80 ns an Acknowledge BIT High-speed mode, CB – 400pF max 20 160 ns Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns tFCL Fall Time of SCL Signal High-speed mode, CB – 100pF max 10 40 ns High-speed mode, CB – 400pF max 20 80 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns tRDA Rise Time of SDA Signal High-speed mode, CB – 100pF max 10 80 ns High-speed mode, CB – 400pF max 20 160 ns Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns tFDA Fall Time of SDA Signal High-speed mode, CB – 100pF max 10 80 ns High-speed mode, CB – 400pF max 20 160 ns Standard mode 4 μs tSU, tSTO Setup Time for STOP Condition Fast mode 600 ns High-speed mode 160 ns CB Capacitive Load for SDA and SCL 400 pF I 2C TIMING DIAGRAMS Figure 2. Serial Interface Timing for F/S-Mode Figure 3. Serial Interface Timing for H/S-Mode 6 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS61310 TPS61311 |
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