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UCD74111 Datasheet(PDF) 9 Page - Texas Instruments

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Part # UCD74111
Description  High-Current, Synchronous Buck Power Stage
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

UCD74111 Datasheet(HTML) 9 Page - Texas Instruments

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UCD74111
www.ti.com
SLUSAT8 – OCTOBER 2012
DETAILED DESCRIPTION
Introduction
The UCD74111 is a power stage for synchronous buck converter with current measurement and fault detection
capabilities making it an ideal partner for digital power controllers. This device incorporates two high-current gate
drive stages, two high-performance NexFET power MOSFETs, and sophisticated current measurement circuitry
that allows for the monitoring and reporting of output load current. Two separate fault detection blocks protect the
power stage from excessive load current or short circuits. On-chip thermal shutdown protects the device in case
of severe over-temperature conditions. The device detects faults immediately, truncates the power conversion
cycle in progress, without controller intervention, and asserts a digital fault flag (FLT). An on-chip linear regulator
supplies the gate drive voltage. If desired, this regulator can be disabled and an external gate drive voltage can
be supplied. Mode selection pins allow the device to be used in synchronous mode or independent mode. In
synchronous mode, the high-side and low-side gate timing is controlled by a single PWM input. Anti-cross-
conduction dead-time intervals are applied automatically to the gate drives. The PWM and SRE pins directly
controls the high-side and low-side gate drive signals In independent mode. The automatic dead-time logic is
disabled in this mode. When operating in synchronous mode, the use of the low-side FET can be disabled under
the control of the SRE pin. This feature facilitates start-up into a pre-bias voltage and is also used in some
applications to reduce power consumption at light loads.
PWM Input (PWM)
The PWM input pin accepts the digital signal from the controller that represents the desired high-side FET on-
time duration. This input accepts 3.3-V logic levels, but also tolerates 5-V input levels. The SRE mode pin sets
the behavior of the PWM pin. When the SRE mode pin asserts high, the device goes into in synchronous mode.
In this mode, PWM input signal controls both the timing duration of the high-side gate drive and the low-side gate
drive . When PWM is high, the high-side gate drive (HS Gate) is on and the low-side gate drive is off. When
PWM is low, the high-side gate drive is off and the low-side gate drive is on. Automatic anti-cross-conduction
logic monitors the gate to source voltage of the FETs to verify that the proper FET is turned OFF before the other
FET is turned ON. When the SRE mode pin is asserted low, the device goes into independent mode. In this
mode the PWM input controls the high-side gate drive only. When PWM is high, the high-side gate drive is on.
While in independent mode, the SRE pin directly controls the low-side FET. Independent mode does not activate
any anti-cross-conduction logic. The user must ensure that the PWM and SRE signals do not overlap.
The PWM input supports a tri-state detection feature. It detects when the PWM input signal has entered a tri-
state mode. When the device detects a tri-state mode, both the high-side and low-side gate drive signals remain
OFF. To support this mode, the PMW input pin has an internal pull-up resistor of approximately 50 k
Ω connected
to the 3.3 V input. It also has a 50 k
Ω pull-down resistor to ground. During normal operation, the PWM input
signal swings below 0.8 V and above 2.5 V. If the source driving the PWM pin enters a tri-state or high
impedance state, the internal pull-up/pull-down resistors tends to pull the voltage on the PWM pin to 1.65 V. If
the voltage on the PWM pin remains within the 0.8 V to 2.5 V tri-state detection range for longer than the tri-state
detection hold-off time (tHLD_R), then the device enters tri-state mode and turns both gate drives OFF. This
behavior occurs regardless of the state of the SRE mode and SRE pins. When exiting tri-state mode, PWM
should first be asserted low. This ensures that the bootstrap capacitor is recharged before attempting to turn on
the high-side FET.
The logic threshold of this pin typically exhibits 900 mV of hysteresis to provide noise immunity and ensure glitch-
free operation of the gate drivers.
Copyright © 2012, Texas Instruments Incorporated
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