eroflex Circuit Technology - Advanced Multichip Modules © SCD3369-1 REV C 5/31/00

BLOCK DIAGRAM

Random Access Memory Chips in one MCM

Banks

Interface

±10% Tolerance)

Accesses)

Column-Address Entry

Upper and Lower Byte Control

Interfacing

ACT-D1M96S High Speed

Multichip Module

Features

General Description

The ACT-D1M96S device is a high-speed 96Mbit synchronous dynamic random access memory (SDRAM)

organized as 2 independent 512K X 48 X 2 banks. All inputs and outputs of the ACT-D1M96S are compatible

with the LVTTL interface. All inputs and outputs are synchronized with the CLK input to simplify system design

and enhance use with high-speed microprocessors and caches.

96 MegaBit 3.3V Synchronous DRAM

16

CS1

CLK1

CKE1

DQMU1

DQML1

RAS1

CAS1

WE1

A0-A11

16

16

16

CS2

CLK2

CKE2

DQMU2

DQML2

RAS2

CAS2

WE2

BA0-BA11

16

16

1M X 16 or

512K X 16 X 2 Banks

1M X 16 or

512K X 16 X 2 Banks

1M X 16 or

512K X 16 X 2 Banks

1M X 16 or

512K X 16 X 2 Banks

1M X 16 or

512K X 16 X 2 Banks

1M X 16 or

512K X 16 X 2 Banks

12

12

S

E

C

T

I

O

N

A

S

E

C

T

I

O

N

B