Aeroflex Circuit Technology

SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700

4

Auto Refresh (REFR)

Before performing a REFR, both banks of all 6 chips must be deactivated (placed in precharge). To

enter a REFR command, RAS and CAS must be low and WE must be high upon the rising edge of

CLK (see Table 1). The refresh address is generated internally such that, after 4096 REFR commands,

both banks of all 6 chips of the ACT-D1M96S have been refreshed. The external address and bank

select (A11) are ignored. The execution of a REFR command automatically deactivates both banks

upon completion of the internal auto-refresh cycle, allowing consecutive REFR-only commands to be

executed, if desired, without any intervening DEAC commands. The REFR commands do not

necessarily have to be consecutive, but all 4096 must be completed before

Power Up Initialization

established, a 200µs interval is required (with no inputs other than CLK). After this interval, both banks

of the device must be deactivated. Eight REFR commands must be performed, and the mode register

must be set to complete the device initialization.

General Information for AC Timing Measurements

All specifications referring to READ commands are also valid for READ-P commands unless otherwise

noted. All specifications referring to WRT commands are also valid for WRT-P commands unless

otherwise noted. All specifications referring to consecutive commands are specified as consecutive

commands for the same bank unless otherwise noted.

Note: For all pin references in the General Description, both sections apply. For example, A11 signals

also apply for BA11 signals.

For additional Detail Information regarding the operation of the individual chip (MT48LC1M16A1) see

Micron’s 524,288-WORD BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS

MEMORY Datasheet Revision 8/99 or contact the Aeroflex Sales Department.