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ACT-7000SC-266F17C Datasheet(PDF) 11 Page - Aeroflex Circuit Technology |
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ACT-7000SC-266F17C Datasheet(HTML) 11 Page - Aeroflex Circuit Technology |
11 / 25 page Aeroflex Circuit Technology SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700 11 Primary Write Buffer Writes to secondary cache or external memory, whether cache miss write-backs or stores to uncached or write-through addresses, use the integrated primary write buffer. The write buffer holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in parallel with memory update. For uncached and write-through stores, the write buffer significantly increases performance by decoupling the SysAD bus transfers from the instruction execution stream. System Interface The ACT 7000SC provides a high-performance 64-bit system interface which is compatible with the RM5200 Family and R5000. Unlike the R4000 and R5000 family processors which provide only an integral multiplication factor between SysClock and the pipeline clock, the ACT 7000SC also allows half-integral multipliers, thereby providing greater granularity in the designers choice of pipeline and system interface frequencies. The interface consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit command bus. In addition, there are six handshake signals and six interrupt inputs. The interface has a simple timing specification and is capable of transferring data between the processor and memory at a peak rate of 600 MB/sec with a 75 MHz SysClock. Figure 6 shows a typical embedded system using the ACT 7000SC. This example shows a system with a bank of DRAMs, and an interface ASIC which provides DRAM control as well as an I/O port. System Address/Data Bus The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the ACT 7000SC and the rest of the system. It is protected with an 8-bit parity check bus, SysADC. The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies. The data rate and the bus frequency at which the ACT 7000SC transmits data to the system interface are programmable via boot time mode control bits. Also, the rate at which the processor receives data is fully controlled by the external device. Therefore, either a low cost interface requiring no read or write buffering or a faster, high-performance interface can be designed to communicate with the ACT 7000SC. Again, the system designer has the flexibility to make these price/performance trade-offs. System Command Bus The ACT 7000SC interface has a 9-bit System Command (SysCmd) bus. The command bus indicates whether the SysAD bus carries an address or data. If the SysAD bus carries an address, then the SysCmd bus also indicates what type of transaction is to take place (for example, a read or write). If the SysAD bus carries data, then the SysCmd bus also gives information about the data (for example, this is the last data word transmitted, or the data contains an error). The SysCmd bus is bidirectional to support both processor requests and external requests to the ACT 7000SC. Processor requests are initiated by the ACT 7000SC and responded to by an external device. External requests are issued by an external device and require the ACT 7000SC to respond. The ACT 7000SC supports one to eight byte and 32-byte block transfers on the SysAD bus. In the case of a sub-double-word transfer, the 3 low-order address bits give the byte address of the transfer, and the SysCmd bus indicates the number of bytes being transferred. Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the ACT 7000SC whether it can accept a new read or write PCI Bus XX Control DRAM Latch 72 72 72 25 SysAD Bus SysCmd Memory I/O Controller Flash / Address Boot ROM ACT 7000SC 8 Figure 6 – Typical Embedded System Block Diagram |
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