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1417G4A Datasheet(PDF) 3 Page - Agere Systems |
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1417G4A Datasheet(HTML) 3 Page - Agere Systems |
3 / 10 page 3 Agere Systems Inc. NetLight 1417G4A and 1417H4A Data Sheet ATM/SONET/SDH Transceivers January 2000 Electrostatic Discharge Caution: This device is susceptible to damage as a result of electrostatic discharge (ESD). Take proper precautions during both handling and testing. Follow EIA® Stan- dard EIA-625. Although protection circuitry is designed into the device, take proper precautions to avoid exposure to ESD. Agere Systems employs a human-body model (HBM) for ESD susceptibility testing and protection-design evaluation. ESD voltage thresholds are dependent on the critical parameters used to define the model. A standard HBM (resistance = 1.5 k Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold estab- lished for the 1417G4A and 1417H4A transceivers is ±1000 V. Application Information The 1417 receiver section is a highly sensitive fiber- optic receiver. Although the data outputs are digital logic levels (PECL), the device should be thought of as an analog component. When laying out system appli- cation boards, the 1417 transceiver should receive the same type of consideration one would give to a sensi- tive analog component. Printed-Wiring Board Layout Considerations A fiber-optic receiver employs a very high gain, wide bandwidth transimpedance amplifier. This amplifier detects and amplifies signals that are only tens of nA in amplitude when the receiver is operating near its sensi- tivity limit. Any unwanted signal currents that couple into the receiver circuitry cause a decrease in the receiver's sensitivity and can also degrade the perfor- mance of the receiver's signal detect (SD) circuit. To minimize the coupling of unwanted noise into the receiver, careful attention must be given to the printed- wiring board layout. At a minimum, a double-sided printed-wiring board (PWB) with a large component-side ground plane beneath the transceiver must be used. In applications that include many other high-speed devices, a multi- layer PWB is highly recommended. This permits the placement of power and ground on separate layers, which allows them to be isolated from the signal lines. Multilayer construction also permits the routing of sen- sitive signal traces away from high-level, high-speed signal lines. To minimize the possibility of coupling noise into the receiver section, high-level, high-speed signals such as transmitter inputs and clock lines should be routed as far away as possible from the receiver pins. Noise that couples into the receiver through the power supply pins can also degrade performance. It is recom- mended that the pi filter, shown in Figure 2, be used for both the transmitter and receiver power supplies. Data and Signal Detect Outputs The data and signal detect outputs of the 1417 trans- ceiver are driven by open-emitter NPN transistors, which have an output impedance of approximately 7 Ω. Each output can provide approximately 50 mA maxi- mum current to a 50 Ω load terminated to VCC – 2.0 V. Due to the high switching speeds of ECL outputs, transmission line design must be used to interconnect components. To ensure optimum signal fidelity, both data outputs (RD+/RD–) should be terminated identi- cally. The signal lines connecting the data outputs to the next device should be equal in length and have matched impedances. Controlled impedance stripline or microstrip construction must be used to preserve the quality of the signal into the next component and to minimize reflections back into the receiver, which could degrade its performance. Excessive ringing due to reflections caused by improperly terminated signal lines makes it difficult for the component receiving these signals to decipher the proper logic levels and can cause transitions to occur where none were intended. Also, by minimizing high-frequency ringing, possible EMI problems can be avoided. The signal-detect output is positive ECL (PECL) logic for the 1417G4A and TTL for the 1417H4A. A logic low at this output indicates that the optical signal into the receiver has been interrupted or that the light level has fallen below the minimum signal detect threshold. This output should not be used as an error rate indicator, since its switching threshold is determined only by the magnitude of the incoming optical signal. |
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