88

Agere Systems Inc.

Data Sheet, Rev. 3

June 2001

Two-Cable Transceiver/Arbiter Device

FW802A Low-Power PHY IEEE 1394A-2000

Table 1. Signal Descriptions (continued)

Pin

Signal*

Type

Name/Description

16

LPS

I

LLC or to a pulsed output that is active when the LLC is powered for the

purpose of monitoring the LLC power status. If LPS is inactive for more

than 1.2

µs and less than 25 µs, interface is reset. If LPS is inactive for

greater than 25

µs, the PHY will disable the PHY/Link interface to save

power. FW802A continues its repeater function.

1LREQ

I

Link Request. LREQ is an output from the LLC that requests the PHY to

perform some service. Bus-keeper circuitry is built into this terminal.

44, 45, 46,

47, 48

NC

—

No Connect.

20

PC0

I

Power-Class Indicators. On hardware reset, these inputs set the default

value of the power class indicated during self-ID. These bits can be

21

PC1

22

PC2

19

PD

I

Powerdown. When asserted high, PD turns off all internal circuitry except

the bias-detect circuits that drive the CNA signal. Internal FW802A logic is

kept in the reset state as long as PD is asserted. PD terminal is provided

for backward compatibility. It is recommended that the FW802A be

allowed to manage its own power consumption using suspend/resume in

conjunction with LPS. C/LKON features are defined in 1394a-2000.

57

—

portion of the device.

58

—

plane.

54

R0

I

Current Setting Resistor. An internal reference voltage is applied to a

resistor connected between R0 and R1 to set the operating current and

the cable driver output current. A low temperature-coefficient resistor

(TCR) with a value of 2.49 k

Ω ± 1% should be used to meet the

IEEE 1394-1995 standard requirements for output voltage limits.

55

R1

61

/RESET

I

Reset (Active-Low). When /RESET is asserted low (active), the FW802A

provided, so only an external delay capacitor is required. This input is a

standard logic buffer and can also be driven by an open-drain logic output

buffer.

28

SE

I

Test Mode Control. SE is used during the manufacturing test and should

29

SM

I

Test Mode Control. SM is used during the manufacturing test and should

63

SYSCLK

O

System Clock. SYSCLK provides a 49.152 MHz clock signal, which is

synchronized with the data transfers to the LLC.

36

TPA0+

Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept matched and as short as possible to the

external load resistors and to the cable connector.

41

TPA1+

* Active-low signals are indicated by “/” at the beginning of signal names, within this document.