LCK4953 datasheet(3/6 Pages) AGERE

Part #	LCK4953

Description	Low-Voltage PLL Clock Driver

Download	6 Pages

Scroll/Zoom	100%

Manufacturer	AGERE [Agere Systems]

Direct Link

Logo

3 / 6 page

Agere Systems Inc.

3

Data Sheet

November 2001

Low-Voltage PLL Clock Driver

LCK4953

Absolute Maximum Ratings (continued)

Table 3. dc Characteristics (TA = 0

°C to 70 °C, VDD = 3.3 V ± 5%)

Table 4. PLL Input Reference Characteristics (TA = 0

°C to 70 °C)

Table 5. ac Characteristics (TA = 0

°C to 70 °C, VDD = 3.3 V ± 5%)

Parameter

Symbol

Min

Typ

Max

Unit

Condition

Input High-voltage LVCMOS

Inputs

VIH

2.0

—

3.6

V

—

Input Low-voltage LVCMOS

Inputs

VIL

——

0.8

V

—

Peak-to-peak Input Voltage

PECL_CLK

Vp-p

300

—

1000

mV

—

Common-mode Range

PECL_CLK

VCMR

VDD – 1.5

—

VDD – 0.6

mV

—*

*VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the high input is within

the VCMR range and the input swing lies within the Vp-p specification.

Output High Voltage

VOH

2.4

——

VIOH = –30 mA†

† The LCK4953 outputs can drive series- or parallel-terminated 50

Ω (or 50 Ω to VCC/2) transmission lines on the incident edge.

Output Low Voltage

VOL

——

0.6

V

IOL = 30 mA†

Input Current

IIN

——

±120

µA

—

Input Capacitance

CIN

——

4pF

—

Power Dissipation Capacitance

Cpd

—

12

—

pF

Per output

Maximum Quiescent Supply

Current Non-PLL

IDDQ

——

1mA

All VDD pins except

VDDA‡

‡ Total Power = (IDDPLL + IDDQ + fCV) * V; where f = fref, V = VDDD, C = total load capacitance on all outputs.

Maximum PLL Supply Current

IDDPLL

——

45

mA

VDDA pin only

Parameter

Symbol

Min

Max

Unit

Condition

Reference Input Frequency

fref

25

130

MHz

—

Reference Input Duty Cycle

trefdc

25

75

%

—

Parameter

Symbol

Min

Typ

Max

Unit

Condition

Output Rise/Fall Time

tr, tf

0.10

—

1.0

ns

0.8 V to 2.0 V

Output Duty Cycle

tpw

47

50

53

%

—

Output-to-output Skews

tsk(O)

——

75

ps

—

PLL VCO Lock Range

fVCO

200

—

520

MHz

—

Frequency Output:

Frequency PLL

Bypass Mode

fout

25

50

—

65

130

250

MHz

VCOSEL = 1

VCOSEL = 0

—

Input to Ext_FB Delay (with PLL locked)

tpd (lock)

–75

—

125

ps

tref = 75 MHz

Input to Q Delay

tpd(bypass)

3

—

7

ns

PLL bypassed

Part to Part Delay

1.5

Output Disable Time

tPLZHZ

——

7ns

—

Output Enable Time

tPZL

——

6ns

—

Cycle-to-cycle Jitter (peak-to-peak)

tjitter

——

50

ps

fout > 75 MHz

Similar Part No. - LCK4953

Manufacturer	Part #	Datasheet	Description
Agere Systems	LCK4950	215Kb / 16P	Low-Voltage PLL Clock Driver

More results

Similar Description - LCK4953

Manufacturer	Part #	Datasheet	Description
Pericom Semiconductor C...	PI6C2972	184Kb / 7P	Low Voltage PLL Clock Driver
Motorola, Inc	MPC974	143Kb / 9P	LOW VOLTAGE PLL CLOCK DRIVER
	MPC992	109Kb / 8P	LOW VOLTAGE PLL CLOCK DRIVER
	MPC932	114Kb / 8P	LOW VOLTAGE PLL CLOCK DRIVER
	MPC930	162Kb / 14P	LOW VOLTAGE PLL CLOCK DRIVER
Integrated Device Techn...	IDT5V9351	85Kb / 10P	LOW VOLTAGE PLL CLOCK DRIVER
Agere Systems	LCK4310	126Kb / 10P	Low-Voltage PLL Clock Driver
Motorola, Inc	MPC958	253Kb / 8P	LOW VOLTAGE PLL CLOCK DRIVER
Renesas Technology Corp	MPC9350	478Kb / 13P	Low Voltage PLL Clock Driver 2019
Motorola, Inc	MPC9350	282Kb / 12P	LOW VOLTAGE PLL CLOCK DRIVER
Motorola, Inc	MPC990	146Kb / 9P	LOW VOLTAGE PLL CLOCK DRIVER

More results

LCK4953 Datasheet(PDF) 3 Page - Agere Systems

LCK4953 Datasheet(HTML) 3 Page - Agere Systems

Similar Part No. - LCK4953

Similar Description - LCK4953

Html Pages

1 2 3 4 5 6

Datasheet Download

Link URL