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OR3LP26B Datasheet(PDF) 8 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 8 Page - Agere Systems |
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8 / 184 page  8 8 Lucent Technologies Inc. ORCA OR3LP26B FPSC Data Sheet Embedded Master/Target PCI Interface March 2000 Lucent Technologies Inc. Description (continued) Following design entry, the development system’s map, place, and route tools translate the netlist into a routed FPSC. A static timing analysis tool is provided to deter- mine device speed and a back-annotated netlist can be created to allow simulation. Timing and simulation out- put files from ORCA Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPSC’s internal configuration RAM. When using the bit stream generator, the user selects options that affect the functionality of the FPSC. Com- bined with the front-end tools, ORCA Foundry pro- duces configuration data that implements the various logic and routing options discussed in this data sheet. FPSC Design Kit Development is facilitated by an FPSC Design Kit which, together with ORCA Foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC Configuration Manager, Verilog * and VHDL* gate-level structural netlists, all necessary synthesis libraries, and complete online documentation. The kit's software cou- ples with ORCA Foundry under the control of the ORCA Foundry Control Center (OFCC), providing a seamless FPSC design environment. More information can be obtained by visiting the ORCA website or con- tacting a local sales office, both listed on the last page of this document. FPGA Logic Overview ORCA Series 3 FPGA logic is a new generation of SRAM-based FPGA logic built on the successful Series 2 FPGA line from Lucent Technologies Microelectron- ics Group, with enhancements and innovations geared toward today’s high-speed designs and tomorrow’s sys- tems on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the ORCA Series 2 devices, the Series 3 more than doubles the logic available in each logic block and incorporates sys- tem-level features that can further reduce logic require- ments and increase system speed. ORCA Series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. ORCA Series 3 FPGA logic consists of three basic ele- ments: programmable logic cells (PLCs), programma- ble input/output cells (PICs), and system-level features. An array of PLCs is surrounded by PICs. Each PLC contains a programmable function unit (PFU), a sup- plemental logic and interconnect cell (SLIC), local rout- ing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be per- formed in the SLIC. The PICs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. Some of the system-level functions include the new microprocessor interface (MPI) and the programmable clock manager (PCM). PLC Logic Each PFU within a PLC contains eight 4-input (16-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop that may be used indepen- dently or with arithmetic functions. The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled indepen- dently. LUTs may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. The SLIC is connected to PLC routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT (AOI) to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections to the PFU out- puts make fast, true 3-state buses possible within the FPGA logic, reducing required routing and allowing for real-world system performance. * Verilog and VHDL are registered trademarks of Cadance Design Systems, Inc. |
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