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OR3TP12 Datasheet(PDF) 1 Page - Agere Systems |
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OR3TP12 Datasheet(HTML) 1 Page - Agere Systems |
1 / 128 page Data Sheet March 2000 ORCA® OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface Introduction Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of an FPGA-based design imple- mentation coupled with the high bandwidth of the industry-standard PCI interface. The ORCA OR3TP12 FPSC provides a full-featured 33/50/66 MHz, 32-/64-bit PCI interface, fully designed and tested, in hardware, plus FPGA logic for user-programmable functions. PCI Local Bus PCI local bus, or simply, PCI bus, has become an industry-standard interface protocol for use in appli- cations ranging from desktop PC busing to high- bandwidth backplanes in networking and communi- cations equipment. The PCI bus specification* pro- vides for both 5 V and 3.3 V signaling environments. The PCI interface clock speed is specified in the range from dc to 66 MHz with detailed specifications at 33 MHz and 66 MHz as well as recommendations for 50 MHz operation. Data paths are defined as either 32-bit or 64-bit. These data path and frequency combinations allow for the peak data transfer rates described in Table 1. Table 1. PCI Local Bus Data Rates The PCI bus is electrically specified so that no glue logic is required to interface to the bus—PCI devices interface directly to the PCI bus. Other features include registers for device and subsystem identifica- tion and autoconfiguration, support for 64-bit addressing, and multimaster capability that allows any PCI bus Master access to any PCI bus Target. PCI Bus Core Highlights s Implemented in an ORCA Series 3 base array, dis- placing the bottom four rows of 18 columns. s Core is a well-tested ASIC model. s Fully compliant to Revision 2.1 of PCI Local Bus Specification (and designed for Revision 2.2). * PCI Local Bus Specification Rev. 2.1, PCI SIG, June 1, 1995. Clock Frequency (MHz) Data Path Width (bits) Peak Data Rate (Mbytes) 33 32 132 33 64 264 66 32 264 66 64 528 Table 2. ORCA PCI FPSC Solutions—Available FPGA Resources * The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, clk drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 × 4 RAM (or 512 gates) per PFU. Device Usable Gates* Number of LUTs Number of Registers Max User RAM Max User I/Os Array Size Number of PFUs OR3TP12 30K—60K 2016 2636 32K 187 14 × 18 252 |
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