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OR3TP12 Datasheet(PDF) 3 Page - Agere Systems |
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OR3TP12 Datasheet(HTML) 3 Page - Agere Systems |
3 / 128 page Lucent Technologies Inc. 3 Data Sheet ORCA OR3TP12 FPSC March 2000 Embedded Master/Target PCI Interface List of Figures Figures Page Figures Page Figure 1. OR3TP12 Array....................................... 11 Figure 2. ORCA OR3TP12 PCI FPSC Block Diagram ..................................................... 12 Figure 3. Master Write Single (FIFO Interface, Dual-Port) .................................. 39 Figure 4. Master Write Single (FIFO Interface, Quad-Port)................................. 40 Figure 5. Master Write Single (PCI Bus, 32-Bit).................................................. 40 Figure 6. Master Write Burst (FIFO Interface, Dual-Port) .................................. 41 Figure 7. Master Write Burst (FIFO Interface, Quad-Port)................................. 42 Figure 8. Master Write Burst (PCI Bus, 32-Bit).................................................. 42 Figure 9. Master Read Single (FIFO Interface, Dual-Port) .................................. 46 Figure 10. Master Read Single (FIFO Interface, Quad-Port)................................. 47 Figure 11. Master Read Single (PCI Bus, 32-Bit).................................................. 47 Figure 12. Master Read Burst (FIFO Interface, Dual-Port) .................................. 49 Figure 13. Master Read Burst (FIFO Interface, Quad-Port)................................. 50 Figure 14. Master Read Burst (PCI Bus, 32-Bit).................................................. 51 Figure 15. Target Configuration Write (PCI Bus, 32-Bit).................................................. 57 Figure 16. Target I/O Write, Nondelayed (PCI Bus, 32-Bit).................................................. 58 Figure 17. Target Memory Single Write (PCI Bus, 32-Bit).................................................. 59 Figure 18. Target Write Single (FIFO Interface, Dual-Port) .................................. 60 Figure 19. Target Write Single (FIFO Interface, Quad-Port)................................. 61 Figure 20. Target Memory Write Burst (PCI Bus, 32-Bit).................................................. 62 Figure 21. Target Write Burst (FIFO Interface, Dual-Port) .................................. 63 Figure 22. Target Write Burst (FIFO Interface, Quad-Port) ...................................64 Figure 23. Target Configuration Read (PCI Bus, 32-Bit) ....................................................68 Figure 24. Target I/O Read, Delayed (PCI Bus, 32-Bit) ....................................................69 Figure 25. Target I/O Read, Nondelayed (PCI Bus, 32-Bit) ....................................................70 Figure 26. Target Single Memory Read, Delayed (PCI Bus, 32-Bit) ......................................71 Figure 27. Target Read Single (FIFO Interface, Dual-Port) ....................................72 Figure 28. Target Read Single (FIFO Interface, Quad-Port) ...................................73 Figure 29. Target Memory Read Single, Nondelayed Transaction (PCI Bus, 32-Bit).............74 Figure 30. Target Burst Memory Read, Delayed (PCI Bus, 32-Bit) ......................................75 Figure 31. Target Read Burst (FIFO Interface, Dual-Port) ....................................76 Figure 32. Target Read Burst (FIFO Interface, Quad-Port) ...................................77 Figure 33. Target Memory Burst Read, Nondelayed (PCI Bus, 32-Bit) ................................78 Figure 34. FPSC Block Diagram and Clock Network........................................................81 Figure 35. Serial Configuration Data Format— Autoincrement Mode ..............................................89 Figure 36. Serial Configuration Data Format— Explicit Mode .........................................................89 Figure 37. ac Test Loads ..........................................99 Figure 38. Output Buffer Delays ...............................99 Figure 39. Input Buffer Delays ..................................99 Figure 40. Sinklim (TJ = 25 °C, VDD = 3.3 V).......... 100 Figure 41. Slewlim (TJ = 25 °C, VDD = 3.3 V) ......... 100 Figure 42. Fast (TJ = 25 °C, VDD = 3.3 V) .............. 100 Figure 43. Sinklim (TJ = 125 °C, VDD = 3.0 V)........100 Figure 44. Slewlim (TJ = 125 °C, VDD = 3.0 V) ....... 100 Figure 45. Fast (TJ = 125 °C, VDD = 3.0 V) ............ 100 Figure 46. Package Parasitics ................................ 121 |
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