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SPRUG08 Datasheet(PDF) 5 Page - Texas Instruments |
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SPRUG08 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 214 page DSP Subsystem 2 C64x+ Megamodule L1P Memory Controller (Memory Protect/Bandwidth Mgmt) Instruction Fetch EDMA 3.0 A Register File A31 - A16 A15 - A0 B Register File B31 - B16 B15 - B0 .L1 .S1 .M1 xx xx .D1 C64x+ DSP Core 32K Bytes L1P SRAM/Cache Direct-Mapped 32K Bytes Total L1D SRAM/Cache 2-Way Set Associative PLL1 and PLL1 Controller Semaphore Power-Down and Device Configuration Logic L3 ROM Boot Configuration DDR2 Memory Controller PLL2 Serial RapidIO (2x) TCP2 VCP2 McBSP0 EMAC 10/100/1000 SGMII MDIO Timer [0-5] I2C GPIO16 FSYNC Antenna Interface 32 L1 Data Memory Controller (Memory Protect/Bandwidth Mgmt) DSP Subsystem 1 DSP Subsystem 0 2 McBSP1 16 .D2 .M2 xx xx .S2 .L2 16-/32-bit Instruction Dispatch Instruction Decode Control Registers SPLOOP Buffer In-Circuit Emulation TMS320C6474 www.ti.com SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 1.3 C6474 Functional Block Diagram Figure 1-2 shows the functional block diagram of the C6474 device. Figure 1-2. Functional Block Diagram Copyright © 2008–2011, Texas Instruments Incorporated Features 5 Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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