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100341QC Datasheet(PDF) 4 Page - Fairchild Semiconductor

Part # 100341QC
Description  Low Power 8-Bit Shift Register
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

100341QC Datasheet(HTML) 4 Page - Fairchild Semiconductor

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Commercial Version (Continued)
SOIC and PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Note 5: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.
Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design
Symbol
Parameter
TC = 0°CTC = +25°CTC = +85°C
Units
Conditions
Min
Max
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
425
425
425
MHz
Figures 2, 3
tPLH
Propagation Delay
0.90
1.70
1.00
1.80
1.00
1.90
ns
Figures 1, 3
tPHL
CP to Output
(Note 5)
tTLH
Transition Time
0.35
1.20
0.35
1.20
0.35
1.20
ns
Figures 1, 3
tTHL
20% to 80%, 80% to 20%
tS
Setup Time
Dn, Pn
0.55
0.55
0.55
ns
Sn
1.50
1.50
1.50
Figure 4
tH
Hold Time
Dn, Pn
0.70
0.70
0.70
ns
Sn
0.50
0.50
0.50
tPW(H)
Pulse Width HIGH
CP
2.00
2.00
2.00
ns
Figure 3
tOSHL
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
200
200
200
ps
(Note 6)
Clock to Output Path
tOSLH
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
200
200
200
ps
(Note 6)
Clock to Output Path
tOST
Maximum Skew Opposite Edge
PLCC Only
Output-to-Output Variation
250
250
250
ps
(Note 6)
Clock to Output Path
tps
Maximum Skew
PLCC Only
Pin (Signal) Transition Variation
250
250
250
ps
(Note 6)
Clock to Output Path


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