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AD5687RBRUZ Datasheet(PDF) 6 Page - Analog Devices |
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AD5687RBRUZ Datasheet(HTML) 6 Page - Analog Devices |
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6 / 28 page  AD5689R/AD5687R Data Sheet Rev. 0 | Page 6 of 28 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. 1.8 V ≤ VLOGIC < 2.7 V 2.7V ≤ VLOGIC ≤ 5.5 V Parameter1 Min Max Min Max Unit Description t1 33 20 ns SCLK cycle time t2 16 10 ns SCLK high time t3 16 10 ns SCLK low time t4 15 10 ns SYNC to SCLK falling edge setup time t5 5 5 ns Data setup time t6 5 5 ns Data hold time t7 15 10 ns SCLK falling edge to SYNC rising edge t8 20 20 ns Minimum SYNC high time (update single channel or both channels) t9 16 10 ns SYNC falling edge to SCLK fall ignore t10 25 15 ns LDAC pulse width low t11 30 20 ns SCLK falling edge to LDAC rising edge t12 20 20 ns SCLK falling edge to LDAC falling edge t13 30 30 ns RESET minimum pulse width low t14 30 30 ns RESET pulse activation time Power-Up Time 4.5 4.5 µs Time that is required to exit power-down and enter normal mode of operation; 24th clock edge to 90% of DAC midscale value with output unloaded 1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 2.7 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested. Figure 2. Serial Write Operation t4 t3 SCLK SYNC SDIN t1 t2 t5 t6 t7 t8 DB23 t9 t10 t11 LDAC1 LDAC2 t12 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. RESET t13 t14 VOUTX DB0 |
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