AD9508PCBZ datasheet(7/40 Pages) AD

Part #	AD9508PCBZ

Description	1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

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Data Sheet

AD9508

Rev. A | Page 7 of 40

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

As Output

Output Voltage

Logic 1

VDD − 0.4

V

1 mA load current

Logic 0

0.4

V

1 mA load current

SDO

Output Voltage

Logic 1

VDD − 0.4

V

1 mA load current

Logic 0

0.4

V

1 mA load current

TIMING

SCLK

Clock Rate, 1/tCLK

30

MHz

Pulse Width High, tHIGH

4.6

ns

Pulse Width Low, tLOW

3.5

ns

SDIO to SCLK Setup, tDS

2.9

ns

SCLK to SDIO Hold, tDH

0

ns

SCLK to Valid SDIO and SDO, tDV

15

ns

EE

AA

to SCLK Setup (tS)

CS

3.4

ns

AA

CSEE

AA

to SCLK Hold (tC)

0

ns

AA

CSEE

AA

Minimum Pulse Width High

3.4

ns

SERIAL PORT SPECIFICATIONS—I2C MODE

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL (AS INPUT)

Input Voltage

Logic 1

VDD − 0.4

V

Logic 0

0.4

V

Input Current

−40

0

µA

For VIN = 10% to 90% DVDD3

Hysteresis of Schmitt Trigger Inputs

150

mV

SDA (AS OUTPUT)

Output Logic 0 Voltage

0.4

V

IO = 3 mA

Output Fall Time from VIH (MIN) to VIL (MAX)

250

ns

10 pF ≤ Cb ≤ 400 pF

TIMING

SCL Clock Rate

400

kHz

Bus-Free Time Between a Stop and Start

Condition, tBUF

1.3

µs

Repeated Start Condition Setup Time, tSU; STA

0.6

µs

Repeated Hold Time Start Condition, tHD;STA

0.6

µs

After this period, the first clock pulse is

generated

Stop Condition Setup Time, tSU; STO

0.6

µs

Low Period of the SCL Clock, tLOW

1.3

µs

High Period of the SCL Clock, tHIGH

0.6

µs

Data Setup Time, tSU; DAT

100

ns

Data Hold Time, tHD; DAT

0

0.9

µs

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