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74ACT715-RSC Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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74ACT715-RSC Datasheet(HTML) 11 Page - Fairchild Semiconductor |
11 / 14 page 11 www.fairchildsemi.com Capacitance (Continued) FIGURE 5. AC Specifications Additional Applications Information POWERING UP The ACT715 default value for Bit 10 of the Status Register is 0. This means that when the CLEAR pulse is applied and the registers are initialized by loading the default values the CLOCK is disabled. Before operation can begin, Bit 10 must be changed to a 1 to enable CLOCK. If the default values are needed (no other programming is required) then Figure 6 illustrates a hardwired solution to facilitate the enabling of the CLOCK after power-up. Should control sig- nals be difficult to obtain, Figure 7 illustrates a possible solution to automatically enable the CLOCK upon power- up. Use of the ACT715-R eliminates the need for most of this circuitry. Modifications of the Figure 7 circuit can be made to obtain the lone CLEAR pulse still needed upon power-up. Note that, although during a Vectored Restart none of the preprogrammed registers are affected, some signals are affected for the duration of one frame only. These signals are the Horizontal and Vertical Drive signals. After a Vec- tored Restart the beginning of these signals will occur at the first CLK. The end of the signals will occur as pro- grammed. At the completion of the first frame, the signals will resume to their programmed start and end time. PREPROGRAMMING “ON-THE-FLY” Although the ACT715 and ACT715-R are completely pro- grammable, certain limitations must be set as to when and how the parts can be reprogrammed. Care must be taken when reprogramming any End Time registers to a new value that is lower than the current value. Should the repro- gramming occur when the counters are at a count after the new value but before the old value, then the counters will continue to count up to 4096 before rolling over. For this reason one of the following two precautions are recommended when reprogramming “on-the-fly”. The first recommendation is to reprogram horizontal values during the horizontal blank interval only and/or vertical values dur- ing the vertical blank interval only. Since this would require delicate timing requirements the second recommendation may be more appropriate. The second recommendation is to program a Vectored Restart as the final step of reprogramming. This will ensure that all registers are set to the newly programmed values and that all counters restart at the first CLK position. This will avoid overrunning the counter end times and will main- tain the video integrity. |
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