© 2005 Fairchild Semiconductor Corporation

DS500687

www.fairchildsemi.com

October 2001

Revised May 2005

74ALVC16373

Low Voltage 16-Bit Transparent Latch

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch

Enable (LE) is HIGH. When LE is LOW, the data that meets

the setup time is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH, the

outputs are in a high impedance state.

The 74ALVC16373 is designed for low voltage (1.1V to

The 74ALVC16373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s 3.6V tolerant inputs and outputs

s Power-off high impedance inputs and outputs

s Support live insertion and withdrawal (Note 1)

s Uses patented noise/EMI reduction circuitry

s Latchup conforms to JEDEC JED78

s ESD performance:

Human body model

! 2000V

Machine model

! 200V

s Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Note 1: To ensure the high-impedance state during power up or power

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

Package Number

Package Description

74ALVC16373GX

(Note 2)

BGA54A

(Preliminary)

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74ALVC16373MTD

(Note 3)

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide