© 2001 Fairchild Semiconductor Corporation

DS500713

www.fairchildsemi.com

December 2001

Revised December 2001

74ALVC16839

Low Voltage 20-Bit Selectable Register/Buffer

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16839 contains twenty non-inverting selectable

buffered or registered paths. The device can be configured

to operate in a registered, or flow through buffer mode by

utilizing the register enable (REGE) and Clock (CLK) sig-

nals. The device operates in a 20-bit word wide mode. All

outputs can be placed into 3-STATE through use of the OE

pin. These devices are ideally suited for buffered or regis-

tered 168 pin and 200 pin SDRAM DIMM memory mod-

ules.

The 74ALVC16839 is designed for low voltage (1.65V to

The 74ALVC16839 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s Compatible with PC100 and PC133 DIMM module

specifications

s 3.6V tolerant inputs and outputs

s Power-off high impedance inputs and outputs

s Supports live insertion and withdrawal (Note 1)

s Uses patented noise/EMI reduction circuitry

s Latchup conforms to JEDEC JED78

s ESD performance:

Human body model

> 2000V

Machine model

> 200V

Note 1: To ensure the high-impedance state during power up or power

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Order Number

Package Number

Package Descriptions

74ALVC16839MTD

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names

Description

OE

Output Enable Input (Active LOW)

Inputs

Outputs

CLK

Clock Input

REGE

Register Enable Input