Electronic Components Datasheet Search |
|
74F114 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
|
74F114 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Unit Loading/Fan Out Truth Table H (h) = HIGH Voltage Level L (h) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (one half shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL J1, J2, K1, K2 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Falling Edge) 1.0/8.0 20 µA/−4.8 mA CD Direct Clear Input (Active LOW) 1.0/10.0 20 µA/−6.0 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA Q1, Q2, Q1, Q2 Outputs 50/33.3 −1 mA/20 mA Inputs Outputs SD CD CP JK Q Q L H XXX H L H L XXX L H L L XXX H H HH hh Q0 Q0 HH lh L H HH hl H L HH ll Q0 Q0 |
Similar Part No. - 74F114 |
|
Similar Description - 74F114 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |