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74F160APC Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74F160APC Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page © 2000 Fairchild Semiconductor Corporation DS009485 www.fairchildsemi.com April 1988 Revised September 2000 74F160A • 74F162A Synchronous Presettable BCD Decade Counter General Description The 74F160A and 74F162A are high-speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for applications in pro- grammable dividers. There are two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The F160A has an asyn- chronous Master Reset input that overrides all other inputs and forces the outputs LOW. The F162A has a Synchro- nous Reset input that overrides counting and parallel load- ing and allows all outputs to be simultaneously reset on the rising edge of the clock. The F160A and F162A are high speed versions of the F160 and F162. Features s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 120 MHz Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74F160A 74F162A Order Number Package Number Package Description 74F160ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F160ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F160APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74F162ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F162APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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