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74F533SC Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74F533SC Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2000 Fairchild Semiconductor Corporation DS009548 www.fairchildsemi.com April 1988 Revised October 2000 74F533 Octal Transparent Latch with 3-STATE Outputs General Description The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The 74F533 is the same as the 74F373, except that the outputs are inverted. Features s Eight latches in a single package s 3-STATE outputs for bus interfacing s Inverted version of the 74F373 Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F533SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F533SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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