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2

Unit Loading/Fan Out

Truth Table

(each half)

H

= HIGH Voltage Level

X

= Immaterial

L

= LOW Voltage Level

Z

= High Impedance

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Side A Address Inputs

1.0/1.0

20

µA/−0.6 mA

Side B Address Inputs

1.0/1.0

20

µA/−0.6 mA

Enable Inputs (Active LOW)

1.0/1.0

20

µA/−0.6 mA

Output Enable Inputs (Active LOW)

1.0/1.0

20

µA/−0.6 mA

Polarity Control Inputs

1.0/1.0

20

µA/−0.6 mA

Side A 3-STATE Outputs

150/40 (33.3)

−3 mA/24 mA (20 mA)

Side B 3-STATE Outputs

150/40 (33.3)

−3 mA/24 mA (20 mA)

Function

Inputs

Outputs

OE

E

High Impedance

H

X

X

X

Z

Z

Z

Z

Disable

L

H

X

X

Active HIGH

L

L

L

L

H

L

L

L

Output

L

L

L

H

L

H

L

L

(P

= L)

L

L

H

LLL

H

L

LL

H

H

L

L

L

H

Active LOW

L

L

L

L

L

H

H

H

Output

L

L

L

H

H

L

H

H

(P

= H)

L

L

H

L

H

H

L

H

L

L

H

HHH

H

L