© 2005 Fairchild Semiconductor Corporation

DS500453

www.fairchildsemi.com

June 2000

Revised February 2005

74LCX10

Low Voltage Triple 3-Input NAND Gate

with 5V Tolerant Inputs

General Description

The LCX10 contains three 3-input NAND gates. The inputs

tolerate voltages up to 7V allowing the interface of 5V sys-

tems to 3V systems.

The 74LCX10 is fabricated with advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

s 5V tolerant inputs

s Power down high impedance inputs and outputs

s

s Implements patented noise/EMI reduction circuitry

s Latch-up performance exceeds 500 mA

s ESD performance:

Human body model

! 2000V

Machine model

! 200V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Truth Table

H

HIGH Voltage Level

X

Immaterial

L

LOW Voltage Level

Order Number

Package Number

Package Description

74LCX10M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX10SJ

M14D

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX10MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names

Description

Inputs

Outputs

XX

L

H

XL

X

H

LX

X

H

HHH

L