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HS0-303CEH-Q Datasheet(PDF) 1 Page - Intersil Corporation

Part # HS0-303CEH-Q
Description  Radiation Hardened BiCMOS Dual SPDT Analog Switch
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HS0-303CEH-Q Datasheet(HTML) 1 Page - Intersil Corporation

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1
Radiation Hardened BiCMOS Dual SPDT Analog Switch
HS-303CEH
The HS-303CEH is an analog switch and a monolithic device
that is fabricated using Intersil’s dielectrically isolated
Radiation Hardened Silicon Gate (RSG) process technology to
insure latch-up free operation. It is pinout compatible and
functionally equivalent to the HS-303RH. This switch offers
low-resistance switching performance for analog voltages up
to the supply rails. ON-resistance is low and stays reasonably
constant over the full range of operating voltage and current.
ON-resistance also stays reasonably constant when exposed to
radiation. Break-before-make switching is controlled by 5V
digital inputs. The HS-303CEH can operate with rails of ±15V.
Specifications
The Detailed Electrical Specifications for the HS-303CEH is
contained in SMD 5962-95813. A “hot-link” is provided from
our website for downloading.
Features
• QML, per MIL-PRF-38535
• No latch-up, dielectrically isolated device islands
• Pinout and functionally compatible with intersil HS-303RH
series analog switches
• Analog signal range equal to the supply voltage range
• Low leakage . . . . . . . . . . . . . . . . . . . . . 150nA (max, post-rad)
•Low rON . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Ω (max, post-rad)
• Low standby supply current . . . . . . . ±150µA (max, post-rad)
• Radiation assurance
- High dose rate (50 to 300rad(Si)/s) . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 50krad(Si)*
• Single event effects
- For LET = 60MeV-mg/cm2 at 60° incident angle,
<150pC charge transferred to the output of an off switch
* Product capability established by initial characterization. The
EH version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
FIGURE 2. RECOMMENDED OPERATING AREA IN GREY
N
P
IN
D
S
FIGURE 1. LOGIC CIRCUIT
TABLE 1. TRUTH TABLE
LOGIC
SW1 AND SW2
SW3 AND SW4
0OFF
ON
1ON
OFF
0
2
4
6
8
10
12
14
16
10
11
12
13
14
15
NEGATIVE SUPPLY VOLTAGE (VEE-)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
April 19, 2013
FN8399.1


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