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74LVTH16652 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH16652 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 9 page www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Truth Table (Note 1) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and #2 control pins Pin Names Description A0–A15 Data Register A Inputs/ 3-STATE Outputs B0–B15 Data Register B Inputs/ 3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OEABn, OEBAn Output Enable Inputs Inputs Inputs/Outputs Operating Mode OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 A0 thru A7 B0 thru B7 L H H or L H or L X X Input Input Isolation LH X X Store A and B Data XH H or L X X Input Not Specified Store A, Hold B HH X X Input Output Store A in Both Registers LX H or L X X Not Specified Input Hold A, Store B LL X X Output Input Store B in Both Registers L L X X X L Output Input Real-Time B Data to A Bus L L X H or L X H Store B Data to A Bus H H X X L X Input Output Real-Time A Data to B Bus H H H or L X H X Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus |
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