Electronic Components Datasheet Search |
|
BR24G08FVM-3TR Datasheet(PDF) 4 Page - Rohm |
|
BR24G08FVM-3TR Datasheet(HTML) 4 Page - Rohm |
4 / 36 page Datasheet 4/33 BR24G08-3 09.Mar.2013 Rev.002 ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 www.rohm.com TSZ02201-0R2R0G100190-1-2 Block Diagram Figure 3. Block Diagram Pin Configuration Pin Descriptions Terminal Name Input/ Output Descriptions A0 - Don’t use (1) A1 - Don’t use (1) A2 Input Slave address setting GND - Reference voltage of all input / output, 0V SDA Input/ Output Serial data input serial data output SCL Input Serial clock input WP Input Write protect terminal VCC - Connect the power source. (1)Pins not used as device address may be set to any of High, Low, and High-Z states 8 7 6 5 4 3 2 1 SDA SCL WP VCC GND A2 A1 A0 Address Decoder Word Address Register Data Register Control Circuit High Voltage Generating circuit Power Source Voltage Detection 8bit ACK START STOP 8Kbit EEPROM Array 10bit 2 5 6 VCC SCL GND BR24G08-3 1 3 4 7 8 WP SDA A2 A1 A0 (TOP VIEW) |
Similar Part No. - BR24G08FVM-3TR |
|
Similar Description - BR24G08FVM-3TR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |