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TCC-103C-RT Datasheet(PDF) 8 Page - ON Semiconductor |
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TCC-103C-RT Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 29 page TCC−103 http://onsemi.com 8 Theory of Operation Overview The control IC outputs are directly controlled by programming the three DACs (DAC A, DAC B, and DAC C) through the digital interface. The DACs are 8-bit DACs used in a 7-bit format. The DAC stages are driven from a reference voltage, generating an analog output voltage driving a high-voltage amplifier supplied from the boost converter (see Control IC block diagram − Figure 1). The control IC output voltages are scaled from 0 to 24 V, with 128 steps of 188 mV (2 × 24 V/255 = 0.188235 V). The nominal control IC output can be approximated to 188 mV × (DAC value). For performance optimization the boost output voltage (VHV) can be programmed to levels between 9 V and 24 V via the DAC_boost register (4 bits with 1 V steps). The startup default level for the boosted voltage is VHV = 20 V. For proper operation and to avoid saturation of the output devices and noise issues it is recommended to operate the boosted VHV voltage at least 2 V above the highest programmed VOUT voltage of any of the three outputs. When the DAC output value is set to 00h the corresponding output is disabled and the output is pulled to GND through an effective impedance of less than 800 W. Operating Modes The following operating modes are available: 1. Shutdown Mode: All circuit blocks are off, the DAC outputs are disabled and placed in high Z state and current consumption is limited to minimal leakage current. The shutdown mode is entered upon initial application of AVDD or upon VIO being placed in the low state. The contents of the registers are not maintained in shutdown mode. 2. Startup Mode: Startup is only a transitory mode. Startup mode is entered upon a VIO high state. In startup mode all registers are reset to their default states, the digital interface is functional, the boost converter is activated, outputs OUT A, OUT B, and OUT C are disabled and the DAC outputs are placed in a high Z state. Control software can request a full hardware and register reset of the TCC−103 by sending an appropriate PWR_MODE command to direct the chip from either the active mode or the low power mode to the startup mode. From the startup mode the device automatically proceeds to the Active mode. 3. Active Mode: All blocks of the TCC−103 are activated and the DAC outputs are fully controlled through the digital interface. The DAC settings can be dynamically modified and the HV outputs will be adjusted according to the specified timing diagrams. Each DAC can be individually controlled and/or switched off according to application requirements. Active mode is automatically entered from the startup mode. Active mode can also be entered from the low power mode under control software command. 4. Low Power Mode: In low power mode the serial interface is enabled, the DAC outputs are disabled and are placed in a high Z state and the boost voltage circuit is disabled. Control software can request to enter the low power mode from the active mode by sending an appropriate PWR_MODE command. The contents of all registers are maintained in the low power mode. AVDD Power-On Reset Upon application of AVDD the TCC−103 will be in shutdown mode. All circuit blocks are off and the chip draws only minimal leakage current. VIO Power-On Reset and Startup Conditions A high level on VIO places the chip in startup mode which provides a power on reset (POR) to the TCC−103. POR resets all registers to their default settings as described in Table 8. VIO POR also resets the serial interface circuitry. POR is not a brown-out detector and VIO needs to be brought back to a low level to enable the POR to trigger again. Table 8. VIO POWER-ON RESET AND STARTUP Register Default State for VIO POR Comment DAC Boost [1011] VHV = 20 V Power Mode [01] > [00] Transitions from SHUTDOWN to STARTUP and then Automatically to ACTIVE Mode DAC Enable [000] VOUT A, B and C Disabled DAC A Output in High-Z Mode DAC B Output in High-Z Mode DAC C Output in High-Z Mode VIO Shutdown A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the registers are not maintained in shutdown mode. |
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Similar Description - TCC-103C-RT |
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