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EPM7128STC100-15N Datasheet(PDF) 45 Page - Altera Corporation

Part # EPM7128STC100-15N
Description  Programmable Logic Device Family
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPM7128STC100-15N Datasheet(HTML) 45 Page - Altera Corporation

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Altera Corporation
45
MAX 7000 Programmable Logic Device Family Data Sheet
Table 32. EPM7128S Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-15
Min
Max
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.2
0.5
0.5
2.0
ns
tIO
I/O input pad and buffer delay
0.2
0.5
0.5
2.0
ns
tFIN
Fast input delay
2.6
1.0
1.0
2.0
ns
tSEXP
Shared expander delay
3.7
4.0
5.0
8.0
ns
tPEXP
Parallel expander delay
1.1
0.8
0.8
1.0
ns
tLAD
Logic array delay
3.0
3.0
5.0
6.0
ns
tLAC
Logic control array delay
3.0
3.0
5.0
6.0
ns
tIOE
Internal output enable delay
0.7
2.0
2.0
3.0
ns
tOD1
Output buffer and pad delay
C1 = 35 pF
0.4
2.0
1.5
4.0
ns
tOD2
Output buffer and pad delay
C1 = 35 pF (6)
0.9
2.5
2.0
5.0
ns
tOD3
Output buffer and pad delay
C1 = 35 pF
5.4
7.0
5.5
8.0
ns
tZX1
Output buffer enable delay
C1 = 35 pF
4.0
4.0
5.0
6.0
ns
tZX2
Output buffer enable delay
C1 = 35 pF (6)
4.5
4.5
5.5
7.0
ns
tZX3
Output buffer enable delay
C1 = 35 pF
9.0
9.0
9.0
10.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
4.0
4.0
5.0
6.0
ns
tSU
Register setup time
1.0
3.0
2.0
4.0
ns
tH
Register hold time
1.7
2.0
5.0
4.0
ns
tFSU
Register setup time of fast
input
1.9
3.0
3.0
2.0
ns
tFH
Register hold time of fast
input
0.6
0.5
0.5
1.0
ns
tRD
Register delay
1.4
1.0
2.0
1.0
ns
tCOMB
Combinatorial delay
1.0
1.0
2.0
1.0
ns
tIC
Array clock delay
3.1
3.0
5.0
6.0
ns
tEN
Register enable time
3.0
3.0
5.0
6.0
ns
tGLOB
Global control delay
2.0
1.0
1.0
1.0
ns
tPRE
Register preset time
2.4
2.0
3.0
4.0
ns
tCLR
Register clear time
2.4
2.0
3.0
4.0
ns
tPIA
PIA delay
(7)
1.4
1.0
1.0
2.0
ns
tLPA
Low-power adder
(8)
11.0
10.0
11.0
13.0
ns


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