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EPM7128STC100-15N Datasheet(PDF) 36 Page - Altera Corporation |
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EPM7128STC100-15N Datasheet(HTML) 36 Page - Altera Corporation |
36 / 66 page 36 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 24. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit MAX 7000E (-12P) MAX 7000 (-12) MAX 7000E (-12) Min Max Min Max tIN Input pad and buffer delay 1.0 2.0 ns tIO I/O input pad and buffer delay 1.0 2.0 ns tFIN Fast input delay (2) 1.0 1.0 ns tSEXP Shared expander delay 7.0 7.0 ns tPEXP Parallel expander delay 1.0 1.0 ns tLAD Logic array delay 7.0 5.0 ns tLAC Logic control array delay 5.0 5.0 ns tIOE Internal output enable delay (2) 2.0 2.0 ns tOD1 Output buffer and pad delay Slow slew rate = off VCCIO = 5.0 V C1 = 35 pF 1.0 3.0 ns tOD2 Output buffer and pad delay Slow slew rate = off VCCIO = 3.3 V C1 = 35 pF (7) 2.0 4.0 ns tOD3 Output buffer and pad delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 5.0 7.0 ns tZX1 Output buffer enable delay Slow slew rate = off VCCIO = 5.0 V C1 = 35 pF 6.0 6.0 ns tZX2 Output buffer enable delay Slow slew rate = off VCCIO = 3.3 V C1 = 35 pF (7) 7.0 7.0 ns tZX3 Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 10.0 10.0 ns tXZ Output buffer disable delay C1 = 5 pF 6.0 6.0 ns tSU Register setup time 1.0 4.0 ns tH Register hold time 6.0 4.0 ns tFSU Register setup time of fast input (2) 4.0 2.0 ns tFH Register hold time of fast input (2) 0.0 2.0 ns tRD Register delay 2.0 1.0 ns tCOMB Combinatorial delay 2.0 1.0 ns tIC Array clock delay 5.0 5.0 ns tEN Register enable time 7.0 5.0 ns tGLOB Global control delay 2.0 0.0 ns tPRE Register preset time 4.0 3.0 ns tCLR Register clear time 4.0 3.0 ns tPIA PIA delay 1.0 1.0 ns tLPA Low-power adder (8) 12.0 12.0 ns |
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